JPH02125347A - Data buffer device for cache replace - Google Patents

Abstract

PURPOSE:To improve the processing efficiency by reading access object data in a buffer to transfer it to an MPU at the time of coincidence between a replace address and a new access address of the MPU and data read. CONSTITUTION:A replace address register (REPADR) 11 holds the replace address as the address of cache replace. A replace data buffer (REP buffer) 12 holds data of replace. An address comparing part 13 compares the replace address in the REPADR 11 with contents of the MPU access address corresponding to the replace address. When the comparison in the address comparing part 13 results in coincidence and data read is indicated, a data transfer control part 14 reads access object data in the REP buffer 12 and transfers it to an MPU 20. Thus, data of replace can be read without waiting for the end of the replace processing in a cache memory device 30.

Description

[Detailed Description of the Invention] [Summary] Regarding a data buffer device for cache replacement that guarantees access to read the data being replaced by a cache memory device, the data buffer device for cache replacement can read the data being replaced without waiting for the end of the replacement to A data buffer device for cache replacement that guarantees newly activated access to read the data being replaced from an MPU while the cache memory device is being replaced. , a register that holds the replace address during cache replacement, a replace data buffer that holds the data that is being replaced, and an address comparison unit that compares the replace address with the new access address of the MPU. In this case, a data transfer control unit is provided to read the access target data in the buffer and transfer it to the MPU.

[Industrial application field]

The present invention relates to a data buffer device for cache replacement that guarantees newly activated access from a processor to read data being replaced while a cache memory device of an information processing device is being replaced.

[Conventional technology]

A cache memory device is a small-capacity, high-speed memory device that is installed to adjust the speed difference between the main memory device and the processor, but in recent years, with the significant improvement in performance in the field of small computers, cache memory The importance of equipment has come into focus.

When the processor accesses the main memory device, it first accesses the cache memory device, and when a hit occurs, reads or writes to that address area. Thereby, data paste/write processing can be performed at high speed. When a miss hint occurs in the cache memory device,
A replacement process is performed in which a program with a lower possibility of access is evicted from the cache memory device to create an empty block, and a new block to be accessed is stored therein.

Hereinafter, a conventional cache memory device and its operation will be described with reference to FIGS. 5 to 7, taking a direct mapping cache memory device as an example.

FIG. 5 is a block diagram showing the configuration of a conventional cache memory device. In the figure, 20 is a processor (hereinafter referred to as MPU), and 30 is a cache memory device. Note that lowercase numbers displayed in each component and route in the diagram indicate the number of bits of data.

In the MPU 20, 21 is an MPU access address register (hereinafter referred to as MPUADR) in which the access address of the MPU 20 is stored. The MPU access address is θ ~ 31032 bits, the 17 bits 15 to 31 form the upper address, and the lower 11 bits 4 to 14 form the C address.
The lower 2 to 14th 13 bits form the CACHE access address.

In the cache memory device 30, 31 is a TAG memory, which has entries at 2, each entry storing an upper address (15 to 31 bits) of the MPU access address.

32 is a through latch that receives the CACHE address of the lower 4 to 14 bits from the MPU access address, and
When a replace signal (hereinafter referred to as REP signal) issued by 20 is added, this cache address is latched, and otherwise it is passed through and stored in the TAG memory 31.
and added to the data memory described later.

33 is an address comparison section, MPUADR21 and TAG
The upper address (15 to 31 bits) of the MPU access address read from the memory 31 is compared, and when they match, a HIT signal is output.

This HIT signal generates a response signal that responds to the MPU 20 that the access has been performed normally.

34 is a data memory, which is a RAM having a long word (4 byte) width and a capacity of 32 KB, and in which cache data is stored.

35 is an address counter which receives bit 2 and pit 3 of MPUADR 21 and stores 4-byte data (
The address bits indicating the address of the longword are counted during replacement.

36 is an address selector, and when receiving the REP signal,
That is, at the time of replacement, the address bits (2 bits) output by the address count 35 are selected, and when the REP signal is off, that is, at the time of normal access other than replacement, bits 2 and 3 of the MPUADR 21 are selected.

37 is a transceiver, and two drivers 371 and 37
2, and performs data transfer between the MPU data bus 38 and the data memory 34, which performs data transfer between the MPU 20 and the data memory 34.
Connect HE data bus 39. Driver 371 is CA
The data on the CHE data bus is sent to the MPU data bus 38, and the driver 372 sends the data on the MPU data bus 38 to the CACHE data bus 39.

Next, the buffer control operation shown in FIG. 5 will be explained separately for when the MPU access address hits the cache memory and when it misses.

(a) Operation when the cache memory is hit The operation when the MPU access address hits the cache memory will be explained with reference to the operation timing chart of FIG.

At the time of access activation, the CACHE address (lower 4 to 14 bits) in the MPU access address stored in the MPUADR 21 is added to the through latch 32 by the address strobe (■ in Fig. 6) issued by the MPU 30 (Fig. 6). ■).

Since the REP signal sent by the MPU 20 is off when access is activated, the CACHE address is stored in the through latch 22.
is added to the TAG memory 31 (6th
■) in the figure. Note that the first MPU access address is a read address, and the next is a write address.

The TAG memory 31 reads the data accessed by the input CACHE address, that is, the upper address (15 to 31 bits) of the MPU access address, and adds it to the address comparator 23.

The address comparison unit 33 compares the upper address of the MPU access address inputted from the TAG memory 31 and the MPUAD.
The upper address of the MPU access address read from R21 is compared, and when the two match, the MPU 20 is notified that the cache memory has been hit. MPU
20 is when the cache memory is hinted, the MPU
A cache data write enable signal (hereinafter referred to as cache data WE signal) is generated in synchronization with the write address in the access address (Fig. 6).
The EP signal is held off.

Furthermore, when the cache memory is hit, no replacement is performed, so the TAG write signal (indicated by the TAG WT times signal) for writing the upper bits of the MPU access address to the TAG memory 31 is not generated (the 6th (■ in FIG. 6), and the output of the address counter 35 is not used or is not activated (■ in FIG. 6).

When the REP signal is off, that is, when the cache memory is hit, the address selector 36
Select hit 2 and bit 3 of R31. Bits 2 and 3 of the selected MPU access address are combined with the lower 4 to 14 bits from the through latch 32 and added to the data memory 34 as a 13-bit CACHE access address 2 to 14. This C
Data memory 34 is accessed by the ACHE access address.

The data memory 34 takes out the data (4-byte width) accessed by the CACHE access address, and when reading, the CACHE data bus 39→driver 371→M
It is transferred to the MPU 20 via the route of the PU data bus 38 (Fig.
→MPU data bus 38 → driver 371 → CACHE
The data added to the data memory 34 through the path of the data bus 39 is written to the CACHE access address entry on the data memory 34 at the timing when the cache data WE signal becomes low level.

As described above, when a cache memory is hit, the data memory 34 is accessed and read/write is performed immediately, so that read/write processing can be performed at high speed.

(bl Operation MP when there is a miss hint in cache memory
The operation when the U access address misses the cache memory will be explained with reference to the operation timing chart of FIG.

As in the case of the hit operation in (a) above, when access is started, the address strobe issued by the MPU 20 (before time 10 of Φ in FIG. 7) causes the CACHE in the MPU access address stored in the MPUADR 21 to be The address (lower 4 to 14 bits) is added to the through latch 32 (before time 10 in Figure 7). R when starting access
Since the EP signal is off, the CACHE address passes through the through latch 32 and is added to the TAG memory 31 (before time 10 in FIG. 7).

The TAG memory 31 stores addresses higher than the input CACHE address (15 to 31) of the MPU access address.
bit) and sends it to the address comparison section 33. The address comparison unit 33 includes the TAG memory 31 and the MPUADR.
Both upper addresses of the MPU access address inputted from 21 are compared, and if they do not match, the MPU 20 is notified that there has been a miss in the cache memory.

When there is a miss in the cache memory, the MPU 20 turns on the REP signal to perform the replacement process (time 10 in FIG. 7) and starts controlling the transfer of one block (16 bytes) to the main memory device (not shown). do.

When the REP signal is turned on, the through latch 32 latches the CACHE address being input (after time 10 in Figure 7).

On the other hand, the selector 36 selects the output of the address counter 35 when the REP signal is turned on.

The address counter 35 counts up bits 2 and 3 of the MPU access address of the MPUADR 31, and sequentially outputs the count values (01, 10°, 11.00) (■ in FIG. 7).

The MPU 20 synchronizes with the MPU address strobe.
The AGWT signal is generated and added to the TAG memory 31 (■ in FIG. 7). As a result, the MP in MPUADR21
The upper address (15 to 31 bits) of the U access address is written to the CACHE address entry on the TAG memory 31.

Furthermore, the MPU 20 uses the nibble mode of the main memory device (not shown) to extract one block of replacement data in four bytes each, and transfers it to the data memory 34 (■ in FIG. 7). In synchronization with the byte data transfer, the cache data WE signal is added to the data memory 34 (■ in FIG. 7). Note that the above-mentioned counting operation of the address counter 35, each 4-byte data transfer, and the sending of the cache data WE are performed in synchronization.

On the other hand, the 2-bit output of the address counter 35 selected by the address selector 36 is combined with the CACHE address (4 to 14 bits) latched by the through latch 32, and the 13-bit CACHE access of the lower 2 to 14 bits of the MPU access address is The address is added to the data memory 34. This CACHE access address sequentially accesses four data entries (one block of 16 bytes) in units of 4 bytes from the CAC/IE address.

As a result, four pieces of 4-byte data (data for one block) transferred from the main memory device (not shown) are stored in the four data entries on the data memory 34 corresponding to the CACHE access address.

The first 4 bytes of the replacement data are the data to be accessed due to a mishit, so the transceiver 3
7 sends the first 4 bytes of the 16 bytes of replacement data transferred from the main memory device to the MPU 20 via the route of CACHE data bus→driver 371→MPU data bus 38 (■ in FIG. 7).

The MPU 20 controls the bus cycle to end after sampling this 4-byte data.

After T when the replacement is performed, the cache memory device 30 becomes busy and access is stopped. Therefore, the MPU 20 can restart the bus cycle, but if the access is for reference, the cache memory device 30 will be in a waiting state until the replacement is completed.
Access is activated 7 after the replacement is completed.

As described above, when a cache memory miss occurs, replacement processing is performed.

[Problem to be solved by the invention]

As described above, in the conventional cache memory control system, when a cache memory miss occurs and replacement processing is being performed, the cache memory cannot be referenced and the cache memory remains in a waiting state until the replacement is completed.

This causes a problem of unnecessary waiting time and reduced processing efficiency. In particular, this problem has become more apparent as there has been a demand for faster processing in the field of small computers in recent years.

The present invention improves processing efficiency by reading the data being replaced and transferring it to the processor 20 without waiting for the end of the replacement when the next access to the cache memory during replacement is a read and the block being replaced. An object of the present invention is to provide a data buffer device for cache replacement which is improved so as to improve the performance.

[Means to solve the problem]

A program has the property that it rarely makes large branches during its execution, and the address of the program it uses often moves sequentially in time from the previous address to the next address. This is called the locality of the program's behavior characteristics.

Cache memory originally takes advantage of the locality of the program's operating characteristics, and stores data at addresses near the most recently accessed address. This increases the possibility that the MPU access address will hit the cache memory. In this case, the possibility that data in the replaced block will be accessed is considered to be particularly high due to the locality of the operating characteristics of the program.

The present invention focuses on this point and makes it possible to transfer the data during replacement when data in a replaced block is accessed.

Hereinafter, the means adopted by the present invention to solve the above-mentioned problems will be explained with reference to FIG. FIG. 1 is a block diagram showing the basic configuration of the present invention.

In FIG. 1, lO is the data buffer device of the present invention;
20 is a processor (indicated by MPU).

In the MPU 20, 21 is an MPU access address register (indicated by MAADR) in which the access address of the MPU 20 is stored.

In the data buffer device 10, 11 is a replace address register (hereinafter referred to as REPADR), which holds a replace address at an address during cache replacement.

12 is a replacement data buffer (hereinafter referred to as REP buffer), which holds data being replaced.

13 is an address comparison unit that compares the replacement address of REPADRI 1 and the MPU corresponding to the replacement address.
Compare the contents of access addresses.

14 is a data transfer control unit which reads the access target data in the REP buffer 12 when the addresses match in the address comparison unit 13 and is read, and sends the data to the MPU 2.
Controls transfer to 0.

30 is a cache memory device. The contents of this cache memory device 30 are TAG memory 31, through latch 32, address comparator 33, and data memory 3.
4. The address counter 35, address selector 36, transceiver 37, drivers 371, 372, MPU data bus 38, CACHE data bus 39, etc. are as explained in FIG. 5, so their explanation will be omitted.

[For production]

The operation of the present invention shown in FIG. 1 will be explained with reference to the operation timing chart of FIG.

The operations performed by ■ to ■ in the operation timing chart of FIG. 2 are operations performed by the conventional cache memory device 30.

That is, the address strobe (
2), the CACHE address portion of the MPU access address stored in the MPUADR 21 is added to the through latch 32 by the MPUADR 21 (10 time points before (2) in FIG. 2). The CAC) IB address passes through the through latch 32 and is added to the TAG memory 31 (before time 10 in Figure 2).

The TAG memory 31 reads the higher address of the MPU address from the input CACHE address and sends it to the address comparison section 33 . The address comparison unit 33 compares both upper addresses of the MPU access address inputted from the TAG memory 31 and the MPUADR 21, and when the two do not match, notifies the MPU 20 that there has been a miss in the cache memory.

When there is a miss in the cache memory, the MPU 20 turns on the REP signal to perform a replacement process (at time T0 in FIG. 2), and starts data transfer control in transfer units to the main memory device (not shown).

When the REP signal is turned on, the through latch 32 latches the CACHE address being input (after time 10 in Figure 2).

On the other hand, the address selector 36 selects the output of the address counter 35 when the REP signal is turned on. The address counter 35 counts the lower bits of the MPU access address of the MPUADR 31, and
The lower bit value of the CACHE access address for accessing is output (■ in FIG. 2).

The MPU 20 synchronizes with the MPU address strobe.
The AGWT signal is generated and added to the TAG memory 31 (■ in FIG. 2). As a result, the MP in MPUADR21
The upper address of the U access address is the TAG memory 31
written to the CACHE address entry above.

Furthermore, the MPU 20 extracts data in units of transfer from a main memory device (not shown) and transfers it to the data memory 34 (
■) in Figure 2). At the same time, a cache data WE signal is added to the data memory 34 in synchronization with the data transfer of each transfer unit (■ in FIG. 2). Note that the counting operation of the address counter 35 described above, each transfer unit data transfer, and the sending of the cache data WE signal are performed in synchronization.

On the other hand, the lower bit output of the address counter 35 selected by the address selector 36 is combined with the CACHE address latched by the through latch 32, and the CACHE address is
It becomes an access address and is added to the data memory 34.

As a result, the data memory 34 stores the replacement data transferred from the main memory device in transfer units (
The figure shows a case where the replacement data consists of four transfer units).

The transceiver 37 sends the replacement data portion of the first transferred transfer unit to the MPU 20 . MPU20
After receiving this transfer unit of data, the bus ends the subsequent bus cycle ((2) in FIG. 2).

In synchronization with the transfer of replacement data to the data memory 34 of the conventional cache memory device described above, the same replacement data is sequentially transferred to the REP buffer 12 for each continuous transmission unit.
(■, [phase], ■, in Figure 2)
■).

Also, the address being replaced (replacement address)
is held in REPADRI 1.

When the first access is completed, the MPU 20 starts the next MP
5 access is started using the U access address, but since the cache memory device 30 is undergoing the above-mentioned replacement process, it cannot be accessed.

However, in the case of the present invention, the content of the next MPU access address in MPUADR21 is
The content of the replace address in R11 is compared by the address comparison unit 13.

The address comparison unit 13 notifies the data transfer control unit 14 of the comparison result of the contents of both.

The data transfer control unit 14 reads the access target data in the REP buffer 12 and sends the MPU 2
Transfer to 0.

If the addresses cannot match in the address comparison unit 13, or even if there is a match, when writing, the REP buffer 1
The data to be accessed in MPU 2 is not transferred to MPU 20.

As mentioned above, the REP that holds the data being replaced
Since the buffer 12 is provided so that it can be accessed even during replacement, the data being replaced can be read by accessing the REP buffer 12 using the MPU access address.

This makes it possible to read the data being replaced without waiting for the end of the replacement process in the cache memory device 3o, eliminating unnecessary waiting time and allowing MP
The processing efficiency of U20 can be improved.

[Example] An example of the present invention will be described with reference to FIGS. 3 to 5. FIG. 3 is an explanatory diagram of the configuration of an embodiment of the present invention, and FIG. 4 is an operation timing chart of the embodiment. The conventional cache memory device 20 shown in FIG. 5 is as described above.

In the following embodiment, it is assumed that the unit of data transfer at the time of replacement is 4 bytes, and replacement is performed in units of blocks each consisting of 16 bytes.

(A) Configuration of Embodiment In FIG. 3, data buffer device 10. Replace address register (REPADR) 11゜Replace address register (REP buffer) 12, address comparison section 13. Data transfer control unit 14゜processor (MP
U)20. MPU access address register (MPUA
DR) 21 and cache memory device 30,
This is as explained in FIG.

Furthermore, the TAG memory 31 . Through latch 32. Address comparison section 33. Data memory 34. Address counter 35, address selector 36. Transceiver 37° driver 371, 372. M
The PU data bus 38 and the CACHE data bus 39 are as described in FIG. Note that the lowercase numbers shown in the figure indicate the number of bits of each data.

40 is a main memory control unit which controls access to the main memory and performs data reading/writing.

In the data buffer device 10, REPADRll is configured with a through launch, and MPUADR31 is connected to the D terminal.
The MPU access address of 4 to 31 bits is inputted from the MPU access address, and the REP signal is inputted to the H (Hold) terminal. When the REP signal is off, the MPU access address passes through the through latch, and when the REP signal is turned on, the MPU access address at that time is launched.

The REP buffer 12 stores four 4-byte wide data entries.
Each block (16 bytes) of replacement data is held. In this REP buffer 12,
A decoder 121 decodes the output of the address counter 36 of the cache memory device 30 and generates access signals for accessing the four data entries of the RFP buffer 12.

122°~122. is a JK-type flip-flop (hereinafter referred to as JKFF), which is provided at the data entry (4 pieces) of the REP buffer 12, and a flag (indicated by ■.~V) indicating the validity/invalidity of the data entry is set. be done. Each JKFF 122o~122. An inverted signal of the REP signal (indicated by *REP) is commonly input to the terminal, and each access signal from the decoder 121 is input to the J terminal. When both the REP signal and the decode signal are on, the JKFF or flag is on (
When the decode signal is OFF, the JKFF, that is, the flag, becomes OFF (L level) to indicate that the data entry is invalid.

Each of these flags (VO to ■i) also functions as a hold signal for the corresponding through latch (described next).

123°～123. are through launches and function as four data entries in the REP buffer 12. Each through latch 123°~123. The replacement data from the main memory control unit 12 is input to the D terminal of , and the corresponding JKFF 122° to 122. A hold signal (flags v0 to V3) is input from. When the hold signal is turned on, that is, the flag is turned on, replacement data (4 bytes) is latched into the corresponding through latch.

124 is a multiplexer (hereinafter referred to as MPX) which selects and outputs one of the through latches 123° to 1233, that is, one of the data entries. 125 is an inverter,
Inverts the REP signal and generates the *RFP signal, JKF
F 122° to 122°, supplied to the terminal.

In the data transfer control unit 14, 141 is a decoder;
Bits 2 and 3 of the MPU access address of the MPUADR 31 are decoded to generate a select signal that sequentially selects 1204 data entries in the REP buffer.

142 is a multiplexer (hereinafter referred to as MPX) which receives the select signal from the decoder 141 and outputs the JKFF122
Select the flag to be output from ゜ to 1223. This selected flag is used as a valid/no indication signal (hereinafter referred to as a VALID signal) of the selected data entry.

A driver 143 outputs replacement data for the data entry selected by the MPX 124 to the MPU data bus 38.

144 is an AND circuit that outputs REP, the signal (REP signal delayed by 2 clocks), and HIT from the address comparator 13.
When both the signal and the READ signal indicating read time are on, the driver 143 is activated. In addition, RE
The AD/WRITE signal is sent from the MPU 20.

145 is an AND circuit, ■ALiD from MPX142
Signal, REP, READ signal and address comparison section 13
When both the HIT signals from the terminal are on, a response signal indicating that the access has been performed normally is output.

(B) Operation of the Embodiment The operation of the embodiment shown in FIG. 3 will be explained with reference to the operation timing chart of FIG. 4.

The MPLJ 20 issues an MPU address strobe and an MPU access address for accessing the cache memory device 20 (■, ■ in FIG. 4) in synchronization with the system clock (■ in FIG. 4).

This MPU address (0 to 31 bits) is
Stored in R31.

In the cache memory device 20, the hit determination is performed by the address comparator 33 in the same manner as described above with reference to FIG.

The address comparator 34 notifies the MPU 20 of a miss hint if the upper address of the TAG memory 31 and the upper address (15 to 31 bits) of the MPUADR 31 do not match.

When the MPU 20 receives this miss notification, it turns on the REP signal to perform the replacement process ((■) in FIG. 4), and starts controlling the transfer of one block of replacement data to the main memory control unit 40. This REP signal is
Through latch 32 of cache memory device 30. Address selector 36° REP buffer 12 JKFFl 2
It is applied to each of the terminals 2° to 1223 and the H terminal of the through latch forming the REPADR 11.

Address selector 36 selects the address output by address counter 35 upon receiving the REP signal. The address counter 36 is bit 2 of the MPU access address.
and bit 3, the address (0
1, 10, 11, 00) in two clock cycles (
Figure 4 ■).

Thereafter, the same replacement processing as explained in FIG. 1, FIG. 2, FIG. 5, and FIG. 7 is performed. That is, the upper address of the MPU access address that has missed is written to the TAG memory 31, and the main memory control unit 40 writes 1
The block (16 bytes) of replacement data is transferred in units of 4 bytes and sequentially stored in the data memory 34.

At that time, the MPU access address (address counter 3
The data (4 bytes) accessed by address 5 (rolJ) is sent to the MPU 20 via the driver 371 and the MPU data bus 38 (@ in FIG. 4).
.

The MPU 20 further generates a REP signal that is delayed by 2 clocks (4 byte transfer processing time) from the REP signal, and
It is added to the ND circuits 144 and 145 (■ in FIG. 4).

On the other hand, the decoder 121 of the REP buffer 12 decodes the address of the address counter 36 and generates an access signal for accessing the four data entries of the REP buffer 12. Address value r of address counter 36
oIJ, rlOJ, r11” and “00”,
JKFF122°, 1221.122□ and 122. The decoded access signal is added to the

Upon receiving this access signal, JKFF122o~122,
are turned on in order and the flags vo, V1. v2 and V
, is generated (■ to [phase] in Fig. 4).

These flags v0 to V serve as hold signals to the corresponding through latches 123° to 123. and latches each 4-byte data transferred from the main memory control unit 40 at that time. As a result, the through latch 123° has 4 bits when the address value of the address counter 36 is “00”.
Byte data D0 is latched, and hereafter, through latch 1
23+.

123 and 123. The address value is "Ol""1"
4-byte data D+, 1)g when “0” and “11”
and are latched (@~■ in Fig. 4).

When the MPU access address to be accessed next after a miss is set in MPUADR31, the address comparison unit 13 of the data buffer device 10
1 MPU access address (4 to 31 bits) and RE
The replacement address latched in PADR11 is compared. REPADRII contains the MPU access address (4 to 31) latched when the REP signal was applied.
bits) are retained. When the next MPU access address accesses data in the block being replaced, the address value (4 to 31 bits) is REPA
Since it matches the replacement address of DR11, the address comparator 13 outputs a HiT signal and the AND circuit 144
and 145.

On the other hand, the decoder 141 of the data buffer device 10
Bit 2 in MPU access address of PUADR31
and bit 3, and generates a select signal that selects the four data entries of REP buffer 12 and applies it to MPX 124 and 142.

MPX142 uses this select signal to select JKFF122° to 122. Select flags v0 to v3 to be output,
When the flag is on, a VALID signal is generated and applied to the AND circuit 145.

The AND circuit 145 receives (7) VALI from the MPX 142.
When the D signal, REP signal, READ signal, and HIT signal are all on, a response signal indicating that the access has been performed normally is generated and notified to the MPU 20.

On the other hand, the MPX 124 receives a select signal from the decoder 141, sequentially selects each of the 4-byte replacement data latched in the through latches 123° to 123, and sends the selected data to the driver 143.

Furthermore, the AND circuit 144 outputs the signal to the driver 1 when the RFP, signal, HIT signal, and read signal are all on.
Activate 43.

As a result, 4-byte replacement data at an address matching the MPU access address for the next access is sent from the driver 143 to the MP via the MPU data bus 38.
Transferred to U20. As the MPU access address is shown in Figure 4, the address in the replacement data is "
10" and "01", this address's 4
Byte data is selected and transferred to the MPU 20 (@ in FIG. 4).

The above description has been made using an example in which replace data consisting of one block (16 bytes) is transferred in units of 4 bytes, but the present invention is also applicable to cases in which replace data is transferred in units of transfer other than this. It is. Also,
The REP buffer 12 can also be configured using registers in addition to through latches.

〔Effect of the invention〕

As explained above, according to the present invention, the following effects can be obtained.

(1) A REP buffer is provided to hold the data being replaced so that it can be accessed even during replacement, so even during replacement, the REP buffer can be accessed even during replacement.
By accessing the P buffer, the data being replaced can be read.

(2) Due to (1) above, data being replaced can be read without waiting for the end of replacement processing in the cache memory device, eliminating unnecessary waiting time and improving MPU processing efficiency. .

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the basic configuration of the present invention, FIG. 2 is an operation timing chart of the present invention, FIG. 3 is an explanatory diagram of the configuration of one embodiment of the present invention, and FIG. 4 is an explanatory diagram of the configuration of an embodiment of the present invention. An example operation timing chart, FIG. 5 is an explanatory diagram of a conventional cache memory device, FIG. 6 is an operation timing chart of a conventional cache memory device at the time of cash hit, and FIG. 7 is a cache of a conventional cache memory device. It is an operation timing chart at the time of a mishit. 1 and 3, 10...data buffer device, 11...replace address register (REPADR), 12...replace data buffer (REP buffer), 13...
・Address comparison unit, 14...Data transfer control unit, 20
...Processor (MPU), 21...MPU access address register (MPUADR), 30...
Cache memory device, 31...TAG memory, 32
... Through latch, 33 ... Address comparison section, 34
...Data memory, 35...Address counter, 3
6...Address selector, 37...Transceiver,
38...MPU data bus, 39...CACHE data bus.

Claims (1)

[Claims] 1. During replacement of the cache memory device (30),
A cache replacement data buffer device (10) that guarantees newly activated access from a processor (20) to read data being pre-raced, the device comprising: (a) a replacement address register that holds a replacement address during cache replacement; (11); (b) a replace data buffer (12) that holds the data being replaced; and (c) a new access between the replace address of the replace address register (11) and the processor (20) corresponding to the replace address. (d) Address comparison unit (13) that compares the contents of the address; and (d) Address comparison unit (13) when the addresses match and when reading, the replacement data buffer (13).
2) reads the data to be accessed in the processor (
20) A data buffer device for cache replacement, comprising: a data transfer control unit (14) for transferring data to a data buffer device.