JPH02125515A - Clock generating circuit - Google Patents
Clock generating circuitInfo
- Publication number
- JPH02125515A JPH02125515A JP27974288A JP27974288A JPH02125515A JP H02125515 A JPH02125515 A JP H02125515A JP 27974288 A JP27974288 A JP 27974288A JP 27974288 A JP27974288 A JP 27974288A JP H02125515 A JPH02125515 A JP H02125515A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- output
- output terminal
- counter
- integrator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 15
- 239000003990 capacitor Substances 0.000 abstract description 2
- 230000010354 integration Effects 0.000 abstract 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 230000001934 delay Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はクロック発生回路、特に、入力信号の立上り、
立下り両方のタイミングを回路動作のタイミングとする
ためのクロック発生回路に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a clock generation circuit, in particular, to
The present invention relates to a clock generation circuit that uses both falling timings as timings for circuit operation.
次に従来のクロック発生回路について図面を参照して詳
細に説明する。Next, a conventional clock generation circuit will be explained in detail with reference to the drawings.
第３図は従来のクロック発生回路の一例を示す回路図で
ある。FIG. 3 is a circuit diagram showing an example of a conventional clock generation circuit.
第３図に示すクロック発生回路は、入力信号ａを偶数個
のインバータ１０１〜１０６により遅延させ、この遅延
信号と入力信号ａとの排他的論理和を排他的論理和回路
１１１を用いて取り、第４図に示すような入力信号の立
上り、立下り両方にクロック信号を得ていた。The clock generation circuit shown in FIG. 3 delays an input signal a by an even number of inverters 101 to 106, calculates the exclusive OR of this delayed signal and the input signal a using an exclusive OR circuit 111, and Clock signals were obtained at both the rising and falling edges of the input signal as shown in FIG.
上述した従来のクロック発生回路は、クロックのパルス
幅がインバータの遅延量によって決まるので、これが各
種製造偏差により変化してしまうという欠点があった。The above-described conventional clock generation circuit has the drawback that the pulse width of the clock is determined by the amount of delay of the inverter, and this can vary due to various manufacturing deviations.
さらに、インバータによる遅延量を多くするとクロック
の“０°ルベルの時間が短かくなってしまうので、確実
な動作を得るパルス幅を作ることが容易でないという欠
点があった。Furthermore, if the amount of delay by the inverter is increased, the "0° level" time of the clock becomes shorter, so there is a drawback that it is not easy to create a pulse width for reliable operation.
本発明のクロック発生回路は、
（＾）入力端子に入力端が接続された電圧制御遅延回路
、
（Ｂ）第１の入力端が前記入力端子に接続され、第２の
入力端が前記電圧制御遅延回路の出力端に接続され、出
力端子に出力端が接続された排他的論理和回路、
（Ｃ）前記出力端子に入力端が接続された、第１の時定
数を有する第１の積分器、
（Ｄ）前記第１の積分器の出力端に入力端が接続された
第１のカウンタ、
（Ｅ）前記第１のカウンタの出力端に入力端が接続され
た第１の動作・不動作検出回路、
（Ｆ）前記第１の動作・不動作検出回路の出力端に入力
端が接続され、電源端が第１の電圧源に接続された第１
の電流源、
（Ｇ）前記出力端子に入力端が接続された、前記第］の
時定数より大きい第２の時定数を有する第２の積分器、
（）ｌ）前記第２の積分器の出力端に入力端が接続され
た第２のカウンタ、 ・
（Ｉ）前記第２のカウンタの出力端に入力端が接続され
た第２の動作・不動作検出回路、
（Ｊ）前記第２の動作・不動作検出回路の出力端に入力
端が接続され、電源端が第２の電圧源に接続され、前記
第１の電流源の出力端に出力端が接続された第２の電流
源、
（に）前記第２の電流源の出力端に入力端が接続され、
前記電圧制御遅延回部の制御端に出力端が接続された第
３の積分器。The clock generation circuit of the present invention includes: (^) a voltage controlled delay circuit whose input end is connected to the input terminal; (B) a first input end connected to the input terminal and a second input end connected to the voltage control delay circuit; an exclusive OR circuit connected to the output end of the delay circuit and having an output end connected to the output terminal; (C) a first integrator having a first time constant and having an input end connected to the output terminal; , (D) a first counter whose input end is connected to the output end of the first integrator, (E) a first operation/non-operation whose input end is connected to the output end of the first counter. a detection circuit, (F) a first circuit whose input terminal is connected to the output terminal of the first operation/non-operation detection circuit and whose power supply terminal is connected to a first voltage source;
(G) a second integrator having a second time constant larger than the time constant of the second integrator, the input end of which is connected to the output terminal; a second counter whose input terminal is connected to its output terminal; (I) a second operation/non-operation detection circuit whose input terminal is connected to the output terminal of said second counter; (J) said second counter; a second current source whose input terminal is connected to the output terminal of the operation/non-operation detection circuit, whose power supply terminal is connected to a second voltage source, and whose output terminal is connected to the output terminal of the first current source; (in) an input end is connected to the output end of the second current source,
a third integrator having an output terminal connected to a control terminal of the voltage-controlled delay circuit section;
とを含んで構成される。It consists of:
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing one embodiment of the present invention.
第１図に示すクロック発生回路は、
（Ａ）入力端子１１に入力端が接続された電圧制御遅延
回路２５１、
（Ｂ）第１の入力端が入力端子１１に接続され、第２の
入力端が電圧制御遅延回路２５１の出力端に接続され、
出力端子２１に出力端が接続された排他的論理和回路１
１１、
（Ｃ）出力端子２１に入力端が接続された第１の積分器
２１１、
（Ｄ）積分器２１１の出力端に入力端が接続された第１
のカウンタ２２１、
（Ｅ）カウンタ２２１の出力端に入力端が接続された第
１の動作・不動作検出回路２３１、（Ｆ）動作・不動作
検出回路２３１の出力端に入力端が接続され、電源端が
第１の電圧源ＶＣＣに接続された第１の電流源２４１、
（Ｇ）出力端子２１に入力端が接続された第２の積分器
２１２ 、。The clock generation circuit shown in FIG. 1 includes: (A) a voltage controlled delay circuit 251 whose input terminal is connected to the input terminal 11; (B) a first input terminal connected to the input terminal 11 and a second input terminal is connected to the output terminal of the voltage controlled delay circuit 251,
Exclusive OR circuit 1 whose output terminal is connected to the output terminal 21
11, (C) a first integrator 211 whose input end is connected to the output terminal 21; (D) a first integrator 211 whose input end is connected to the output end of the integrator 211;
(E) a first operation/non-operation detection circuit 231 whose input terminal is connected to the output terminal of the counter 221; (F) a first operation/non-operation detection circuit 231 whose input terminal is connected to the output terminal of the operation/non-operation detection circuit 231; (G) a first current source 241 whose power supply end is connected to the first voltage source VCC; (G) a second integrator 212 whose input end is connected to the output terminal 21;
（Ｉ１）積分器２１２の出力端に入力端が接続された第
２のカウンタ２２２、
（Ｉ）カウンタ２２２の出力端に入力端が接続された第
２の動作・不動作検出回路２３２、（Ｊ）動作・不動作
検出回路２３２の出力端に入力端が接続され、電源端が
第２の電圧源Ｖ５５に接続され、電流源２４１の出力端
に出力端が接続された第２の電流源２４２、
（Ｋ）電流源２４２の出力端に入力端が接続され、電圧
制御遅延回路２５１の制御端に出力端が接続された第３
の積分器２１３、
とを含んで構成される。(I1) a second counter 222 whose input terminal is connected to the output terminal of the integrator 212; (I) a second operation/non-operation detection circuit 232 whose input terminal is connected to the output terminal of the counter 222; (J ) A second current source 242 whose input terminal is connected to the output terminal of the operation/non-operation detection circuit 232, whose power supply terminal is connected to the second voltage source V55, and whose output terminal is connected to the output terminal of the current source 241. , (K) a third circuit whose input terminal is connected to the output terminal of the current source 242 and whose output terminal is connected to the control terminal of the voltage-controlled delay circuit 251;
The integrator 213 is configured to include the following.
積分器２１１の時定数より積分器２１２の時定数の方を
大きく選んである。The time constant of the integrator 212 is selected to be larger than the time constant of the integrator 211.
積分器２１３は波形の平滑を目的としたものである。The integrator 213 is intended to smooth the waveform.
カウンタ２１１が動作しない時（クロックパルス幅が大
）は、電圧制御遅延回路２５１の遅延量を増加さぜ、カ
ウンタ２１２が動作しない時は、電圧制御遅延回路２５
１の遅延量を減少させる。When the counter 211 does not operate (the clock pulse width is large), the delay amount of the voltage controlled delay circuit 251 is increased, and when the counter 212 does not operate, the delay amount of the voltage controlled delay circuit 251 is increased.
Decrease the delay amount of 1.
第２図は第１図に示すクロック発生回路の詳細回路図で
ある。FIG. 2 is a detailed circuit diagram of the clock generation circuit shown in FIG. 1.
電圧制御遅延回路２５１の可変抵抗部にはＮＭＯＳトラ
ンジスタを、積分器２１１．．２１２にはレジスタとキ
ャパシタを使用している。The variable resistance section of the voltage controlled delay circuit 251 includes an NMOS transistor, and the integrator 211 . ．． 212 uses a resistor and a capacitor.
出力信号すは積分器２１］、、２１２を通り、時定数の
小さい積分器２１−１は幅の広いパルスを、時定数の大
きい積分器２１２は幅の狭いパルスを得る。The output signal passes through integrators 21, 212, and the integrator 21-1 with a small time constant obtains a wide pulse, and the integrator 212 with a large time constant obtains a narrow pulse.
カウンタ２２１が動作し７た時は、電流源２／１］をＯ
Ｎさせて積分器２１３の出力を下げ、電圧制御遅延回路
２５１のＮＭＯ３）ランジスタの抵抗値を下げ遅延量を
減少させて、パルス幅を狭くづ”る。When the counter 221 operates and reaches 7, the current source 2/1] is turned off.
N to lower the output of the integrator 213, lower the resistance value of the NMO3) transistor of the voltage control delay circuit 251, reduce the amount of delay, and narrow the pulse width.
カウンタ２２２が動作しない時は、電流源２．１２をＯ
Ｎさせて積分器２１３の出力を上げ、電圧制御遅延回路
２５１のＮＭＯ３Ｉ〜ランジスタカ抵抗値を上げ遅延量
を増大させて、パルス幅を広くする。When counter 222 does not operate, current source 2.12 is turned off.
N to increase the output of the integrator 213, increase the resistance value of NMO3I of the voltage control delay circuit 251, increase the delay amount, and widen the pulse width.
このようにすると、実動作が確実に行なえるパルス幅を
自動的に得ることができる。In this way, it is possible to automatically obtain a pulse width that allows actual operation to be performed reliably.
本発明のクロック発生回路は、２つの積分器の時定数を
適切に選ぶことにより、確実に動作させることのできる
パルス幅のクロックを発生できるという効果がある。The clock generation circuit of the present invention has the advantage that by appropriately selecting the time constants of the two integrators, it is possible to generate a clock with a pulse width that allows reliable operation.
第１図は本発明の一実施例を示すブロック図、第２図は
第１図に示すクロック発生回路の詳細回路図、第３図は
従来の一例を示す回路図、第４図は第３図の動作を示す
波形図である。
１１・・・・・・入力端子、２１・・・・・・高力端子
、１１１−・・・・・排他的論理和回路、２１１〜２１
３・・・・・・積分器、２２１，２２２・・・・・・カ
ウンタ、２３１，２３２・・・・・・動作・不動作検出
回路、２４１．２４２・・・・・・電流源。
ａ・・・・・・入力信号、ｂ・・・・・・出力信号。
第３図
第４図FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a detailed circuit diagram of the clock generation circuit shown in FIG. 1, FIG. 3 is a circuit diagram showing a conventional example, and FIG. FIG. 3 is a waveform chart showing the operation shown in FIG. 11...Input terminal, 21...High strength terminal, 111-...Exclusive OR circuit, 211-21
3... Integrator, 221, 222... Counter, 231, 232... Operation/non-operation detection circuit, 241.242... Current source. a...Input signal, b...Output signal. Figure 3 Figure 4
Claims (1)
、 （Ｂ）第１の入力端が前記入力端子に接続され、第２の
入力端が前記電圧制御遅延回路の出力端に接続され、出
力端子に出力端が接続された排他的論理和回路、 （Ｃ）前記出力端子に入力端が接続された、第１の時定
数を有する第１の積分器、 （Ｄ）前記第１の積分器の出力端に入力端が接続された
第１のカウンタ、 （Ｅ）前記第１のカウンタの出力端に入力端が接続され
た第１の動作・不動作検出回路、 （Ｆ）前記第１の動作・不動作検出回路の出力端に入力
端が接続され、電源端が第１の電圧源に接続された第１
の電流源、 （Ｇ）前記出力端子に入力端が接続された、前記第１の
時定数より大きい第２の時定数を有する第２の積分器、 （Ｈ）前記第２の積分器の出力端に入力端が接続された
第２のカウンタ、 （Ｉ）前記第２のカウンタの出力端に入力端が接続され
た第２の動作・不動作検出回路、 （Ｊ）前記第２の動作・不動作検出回路の出力端に入力
端が接続され、電源端が第２の電圧源に接続され、前記
第１の電流源の出力端に出力端が接続された第２の電流
源、 （Ｋ）前記第２の電流源の出力端に入力端が接続され、
前記電圧制御遅延回路の制御端に出力端が接続された第
３の積分器、 とを含むことを特徴とするクロック発生回路。[Scope of Claims] (A) A voltage controlled delay circuit having an input terminal connected to the input terminal; (B) A first input terminal connected to the input terminal and a second input terminal connected to the voltage controlled delay circuit. (C) a first integrator having a first time constant, whose input terminal is connected to the output terminal; D) a first counter whose input terminal is connected to the output terminal of the first integrator; (E) a first operation/non-operation detection circuit whose input terminal is connected to the output terminal of the first counter. , (F) a first circuit whose input terminal is connected to the output terminal of the first operation/non-operation detection circuit and whose power supply terminal is connected to the first voltage source.
(G) a second integrator having a second time constant greater than the first time constant, the input end of which is connected to the output terminal; (H) the output of the second integrator. a second counter having an input end connected to the second counter; (I) a second operation/non-operation detection circuit having an input end connected to the output end of the second counter; (J) the second operation/non-operation detection circuit; a second current source whose input terminal is connected to the output terminal of the non-operation detection circuit, whose power supply terminal is connected to a second voltage source, and whose output terminal is connected to the output terminal of the first current source, (K ) an input end is connected to the output end of the second current source,
A clock generation circuit comprising: a third integrator having an output terminal connected to a control terminal of the voltage-controlled delay circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27974288A JPH02125515A (en) | 1988-11-04 | 1988-11-04 | Clock generating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27974288A JPH02125515A (en) | 1988-11-04 | 1988-11-04 | Clock generating circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02125515A true JPH02125515A (en) | 1990-05-14 |
Family
ID=17615264
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27974288A Pending JPH02125515A (en) | 1988-11-04 | 1988-11-04 | Clock generating circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02125515A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04329710A (en) * | 1991-04-30 | 1992-11-18 | Nec Corp | Two-multiple circuit |
| US6531904B1 (en) * | 1995-05-24 | 2003-03-11 | Infineon Technologies Ag | Circuit configurations having a delay device, a multiplier, filter and/or a master-slave flip-flop for generating: an output signal being orthogonal to an input signal, an output signal having a frequency being double that of an input signal, or two output signals being orthogonal to one another |
| KR100926684B1 (en) * | 2002-11-15 | 2009-11-17 | 삼성전자주식회사 | Spread Spectrum Clock Generator |
-
1988
- 1988-11-04 JP JP27974288A patent/JPH02125515A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04329710A (en) * | 1991-04-30 | 1992-11-18 | Nec Corp | Two-multiple circuit |
| US6531904B1 (en) * | 1995-05-24 | 2003-03-11 | Infineon Technologies Ag | Circuit configurations having a delay device, a multiplier, filter and/or a master-slave flip-flop for generating: an output signal being orthogonal to an input signal, an output signal having a frequency being double that of an input signal, or two output signals being orthogonal to one another |
| KR100926684B1 (en) * | 2002-11-15 | 2009-11-17 | 삼성전자주식회사 | Spread Spectrum Clock Generator |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH02125515A (en) | Clock generating circuit | |
| JP2677215B2 (en) | Zero volt switch Pulse width modulation type switching regulator control circuit | |
| JPH0472912A (en) | Power-on reset circuit | |
| WO2002015382A2 (en) | Oscillator having reduced sensitivity to supply voltage changes | |
| JPH0595259A (en) | Staircase generating circuit | |
| KR880000916Y1 (en) | Reset delay circuit | |
| JPS6076807A (en) | Clock shaping circuit | |
| JPH0424888B2 (en) | ||
| JPS61254075A (en) | Power source | |
| SU718896A1 (en) | Delay multivibrator | |
| JPH0219649B2 (en) | ||
| KR0118634Y1 (en) | Frequency multiflier | |
| JPS5941641Y2 (en) | Reset signal generation circuit | |
| JPH0212752Y2 (en) | ||
| JPS62139408A (en) | Clock generating circuit | |
| KR940001491Y1 (en) | Output multifunction circuit of photoelectric switch | |
| KR960018856A (en) | Start level adjustment circuit of monitor horizontal oscillation circuit | |
| KR910008955A (en) | Trigger pulse generator | |
| JPH0443356B2 (en) | ||
| JPS63275219A (en) | Multiplication circuit | |
| JPH1084277A (en) | Clock generation circuit | |
| JPH05283994A (en) | Reset circuit | |
| JPH02180420A (en) | Multiplying circuit | |
| JPS62116011A (en) | Pulse generating circuit | |
| JPH0383494U (en) |