JPH0212558A - Inter-processor communication control system - Google Patents

Abstract

PURPOSE:To perform inter-processor communication with simple constitution without lowering the throughput of a processor by transferring data between the processors via a common memory corresponding to the setting condition of a state setting means, and changing the setting condition according to the transfer of the data. CONSTITUTION:Either the processor 110 or 120 makes access to the common memory 140 corresponding to the setting condition of the state setting means 130 on which the states of the processors 110 and 120 are set, and performs the readout/write of the data, and changes the setting condition of the state setting means 130 so as to enable the next processor 120 or 110 to make access to the common memory 140. And the next processor 120 or 110 makes access to the common memory 140 similarly corresponding to the above change, the changes the setting condition of the state setting means 130. Thereby, it is possible to perform the inter-processor communication with simple constitution without lowering the throughput of the processors 110 and 120.

Description

[Detailed Description of the Invention] [Summary] Regarding an inter-processor communication control method for controlling data exchange between a plurality of processors, inter-processor communication is realized with a simple configuration without reducing the processing capacity of the processors. The apparatus is equipped with a state setting means for setting each state of a plurality of processors, and a common memory that can be accessed by each processor, and the common memory is set for each processor according to the setting conditions of the state setting means. and a communication control means for instructing access to the device and setting the state to the state setting means.

[Industrial Application Field] The present invention relates to an inter-pro-sensor communication control system for controlling data exchange between a plurality of pro-sensors.

[Conventional technology]

In a system in which a plurality of processors share and perform processing, processing data is referenced between the processors.

A conventional method for transmitting and receiving data between processors is such that a plurality of processors are prioritized and a processor with a higher priority controls a processor with a lower priority to transmit and receive data.

[Problem to be solved by the invention]

However, in such conventional methods, the controlled processor (low priority processor) interrupts its own processing and performs inter-processor communication in response to a communication request from the control processor (high priority processor). It was necessary to do this.

On the other hand, the control processor also needs to perform processing that takes into consideration the controlled processor.

In this way, in the conventional inter-processor communication control method, the controlled processor responds to the access of the controlling processor.
It is necessary to interrupt the processing of the own device to respond, and it cannot be used in a system that performs real-time processing that is difficult to interrupt.

The present invention solves these conventional problems,
An object of the present invention is to provide an inter-processor communication control method that can realize inter-processor communication with a simple configuration without reducing the processing capacity of the processor.

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of the present invention.

In the figure, each state of a plurality of processors 110 and 120 is set in state setting means 130.

The common memory 140 can be accessed from each processor.

The communication control means 111121 provided in each Brossenna controls the common memory 1 according to the setting conditions of the state setting means 130.
40 is indicated as ↑, and the state setting means 130 sets the state of each processor.

[Function] According to the present invention, one processor accesses the common memory 140, reads and writes data, and the next state setting means 1 so that the processors of the common memory 140 can access the common memory 140.
Change the setting conditions of 30. In response, the next processor similarly accesses the common memory 140 and changes the setting conditions of the state setting means 130.

That is, data between the processors is inherited via the common memory 140 according to the setting conditions of the state setting means 130, and by changing the setting conditions in accordance with the inheritance, each processor becomes autonomous. can control data transfer between them.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention.

In addition, in this embodiment, the state setting means (FIG. 1, 130)
is realized by a flip-flop corresponding to each processor, and the communication control means (111121) is realized by software of each processor.

In the figure, a processor A210 connected to a host device
, and processor B 220 which performs line control, are connected to flip-flops 231 and 233 which can be set and reset to each other. That is, the flip-flop (FFI) 231 can be set by the processor A 210 and reset by the processor B 220, and the flip-flop (FF2) 233 can be set by the processor B 220 and reset by the processor A 210.

Note that the state of each flip-flop 231 and 233 can be detected by each prosensor 210 and 220. That is, for example, each Q output is supplied to processor A 231 and processor B 233, respectively.

Furthermore, each processor 210 and 220 includes a common memory (CM) 24 that can be written to and read from, respectively.
0 is connected.

Here, the shape M(Q
output) and a common memory 2 for each processor 210, 220.
The following table shows the conditional relationships regarding whether or not access to 40 is possible.

As shown in Table 22, flip-flop (FFI) 231
and flip-flop (FF2) 233 are both reset when the power is turned on, and access to the common memory 240 is only permitted from the processor A 210, and data (
initial data) is written to the common memory 240 (■)
.

After writing is completed, the processor A 210 sets the flip-flop (FFI) 231 (■).

Processor B220 monitors the state of each flip-flop, detects that the Q output of flip-flop (FFI) 231 is "l" and the Q output of flip-flop (FF2) 233 is "0", and It is recognized that the memory 240 can now be accessed. Note that at this time, processor A 210 is prohibited from accessing common memory 240.

Processor B 220 reads initial data from common memory 240 and performs processing based on the data. Furthermore, processor B 220 writes data to be notified to processor A 210 in common memory 240 (■).

After writing is completed, the processor B 220 sets the flip-flop (FF2) 233 (■).

Processor A210 monitors the state of each flip-flop, detects that the Q output of flip-flop (FFI) 231 is "l" and the Q output of flip-flop (FF2) 233 is "1", and common It is recognized that the memory 240 can now be accessed. Note that at this time, processor B 220 is prohibited from accessing common memory 240.

Processor A 210 reads data from common memory 240. Further, the processor A210 is the processor B2
If there is data to be notified to 20, it is sent to common memory 2.
Write in 40 (■).

After writing is completed, the processor A 210 resets the flip-flop (FF2) 233 (■).

That is, state (2) has the same conditions as state (2), and processor B 220 can access the common memory 240. When processor B 220 finishes reading data from common memory 240 and writing data to be notified to processor A 210, it sets flip-flop (FF2) 233 (■). Similarly, states (1) and (2) caused by the reset of the flip-flop (FF2) 233 are repeated, and data is transferred between processors via the common memory 240.

Additionally, when an error occurs in the processor B220 due to data loss or other causes, the flip-flop (F
FI) Reset 231 (■).

Therefore, the processor A 210 recognizes from the Q output of the flip-flop (FFI) 231 that the processing of the processor B 220 has become abnormal.

Note that state (2) is the same condition as state (2) at system startup.

In this way, when each state (Q output) of the flywheels 231 and 233 is r'o, OJ, or "ll", the processor A 210 can access the common memory 240, and when it is "10", the processor A210 can access the common memory 240. B
220 can access the common memory 240.

FIG. 3 is a flowchart illustrating an example of the operation of the communication control means (111, 121 in FIG. 1).

FIGS. 3(a) and 3(b) show processor A (FIG. 2, 21
3(C) and (d) show the operation of Processor B (220).

In FIG. 2 and FIGS. 3(a) and 3(b), when the processor A210 is powered on, the flip-flop (
FF2) 233 is reset and initial setting operation is performed.

Subsequently, initial data (line implementation table) required for processing by the processor B 220 is received from the host device, this initial data is written into the common memory 240, and the flip-frosive (FFI) 231 is set. Here, the conditions for allowing access to the common memory 240 are changed, and the processor B 220 can access it.

Processor A210 includes each flip-flop 231.2.
While monitoring the status of 33, the interrupt processing (command processing) shown in FIG. 3(b) is performed. Here, if the flip-flop (FFI) 231 is in the set state (Q output is "1") and the flip-flop (FF2) 233 is in the reset state (Q output is "0") (state ■ in the table), Continue status monitoring (command processing).

When the flip-flop (FF2) 233 becomes set state (Q output is "1") (state ■ in the table), the common memory 24
0 is processed and the flip-flop (FF2) 233 is reset, access to the common memory 240 is transferred to the processor B 220 again, and the process returns to status monitoring.

Furthermore, if the flip-flop (FFI) 231 is in the reset state (Q output is "0") (state ■ in the table), it means that an abnormality has occurred in the processor B 220, so the common memory 240
Write initial data to return to the state at system startup.

Note that when the flip-flop (FFI) 231 is reset due to the occurrence of an abnormality in the processor B 220, the processor B 220 accesses the common memory 240, and the control right of each flip-flop 231 and 233 is also transferred to the processor B 220. be. That is, the flip-flop (FF2) 233 is in the reset state (the state shown in the table ■).
Or, it should have been (■). At this point, along with the reset of the flip-flop (FFI) 231, the flip-flop (FF2) 233 is reset to return to a reliable initial setting state.

In FIGS. 2 and 3(C) and (d), the processor B220 performs a flip-flop (
FFI) 231 and performs initial setting operation.

Subsequently, the state of each flip-flop 231, 233 is monitored until the flip-flop (Fi"1) 231 is in the set state (Q output is "1").

When the flip-flop (FFI) 231 is in the set state (table state ■), it performs processing to receive initial data (line implementation table) from the common memory 240, and permits interrupt processing (line processing) of the processor [3220]. Unmask. Next, it monitors the occurrence of abnormalities associated with line processing, and if an abnormality occurs, the flip-flop (FFI) 2
If you reset 31, the state shown in the table ■) returns to the initial setting state.

Furthermore, in the processor B 220, interrupt processing is permitted upon cancellation of the mask, and interrupt processing (line processing) shown in FIG. 3(d) is started.

In line processing, the line status is read and synchronization detection processing is performed. Further, it is determined whether an error has occurred based on synchronization confirmation, and if an error has occurred, information (abnormality occurrence information) that can be detected in the above-mentioned abnormality occurrence state monitoring is set.

If the synchronization detection is normal, data processing is performed and it is determined whether or not it is necessary to send data to processor A210. If there is transmission data and the flip-flop (FF2) 233 is in the reset state (Q output is "0"), the processor B 220 can access the common memory 240, so it writes the transmission data and transfers the data to the flip-flop (FF2).
F2) Set 233.

When the synchronization detection process is completed, when the abnormality occurrence information is set, when it is unnecessary to send data to the processor A 210, when the flip-flop (FF2) 233 is in the set state (the common memory 240 cannot be accessed),
And when the flip-flop (FF2) 233 is set, the process moves to the next interrupt process.

2, a common memory 240 is provided, and each processor 2
10, 220 can be controlled by flip-flops 231, 2
By determining whether access is possible based on the state of 33, it becomes possible to transfer data between processors with a simple configuration and control method.

〔Effect of the invention〕

As described above, according to the present invention, each processor can transfer data between processors according to their respective processing states, so that line processing that requires real-time processing and cannot be interrupted is possible. It can also be used with processors that perform other tasks.

Therefore, inter-processor communication can be realized with a simple configuration and control without reducing the processing ability of the control processor located above it, which is extremely useful in practice.

, FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 3 is a flowchart illustrating an example of the operation of the communication control means (111, 121 in FIG. 1).

In the figure, 110 and 120 are processors, 111 and 121 are communication control means, 130 are state setting means, 140 are common memory, 210 is processor A1, 220 is processor B1, 231 is a flip-flop (FFI), and 233 is a flip-flop (FF2) , 240 is a common memory (CM).

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention. Pole departure I: 1 city bone pushing “o,,, 7)” 73 Fig. 1 Variant case 1- generation Figure 2

Claims (1)

[Claims] (1) A state setting means (130) in which each state of a plurality of processors (110, 120) is set, and a common memory (140) that can be accessed from each processor, and each processor has the state setting means It is characterized by comprising communication control means (111, 121) that instructs access to the common memory (140) according to the setting conditions of (130) and sets the state of the state setting means (130). An inter-processor communication control method.