JPH0212632Y2 - - Google Patents

Description

[Detailed description of the invention] (a) Field of industrial application The invention relates to an electronic time clock that emits different types of time signal sounds at the hour and half-hour. This invention relates to a clock that reports time based on the above.

(b) Prior art Conventionally, this type of time signal clock was published in Japanese Patent Application Laid-open No. 1983-
There was one disclosed in Publication No. 195188. In addition to the time signal contact mechanism for detecting the hour, this watch has
It had an internal counter synchronized with the indicated time, and half an hour was detected from the time code of the counter.

(c) Problems to be solved by the invention In the conventional example described above, when setting the time such as when the battery is inserted, the timing operation of the internal counter does not follow, so the indicated time and the operation of the counter do not match. Malfunctions sometimes occurred until the operations matched.

(d) Means for Solving the Problems As stated in the claims for utility model registration, the present invention provides a timepiece that performs a time signal operation at least on the hour and half-hour, in accordance with the indicated time. The time reporting operation is started by an output signal from a time reporting contact mechanism that outputs a time reporting start signal at the hour, and the discrimination between the hour and half time is performed by providing a specific code for half time in the time code, and the above-mentioned This solves the problems of the conventional example.

(e) Examples Examples of the present invention will be described below based on the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. 2 is an oscillation circuit that outputs a high frequency signal; 4
10 is a frequency dividing circuit that appropriately divides the high frequency signal from the oscillation circuit 2; 6 is a waveform shaping circuit that shapes the waveform of the frequency-divided signal; 8 is a motor driven by the signal from the waveform shaping circuit 6; A wheel train 12 is driven by a motor 8, and a pointer display 12 is driven by a wheel train 10.

14 is a time signal contact point, as shown in Fig. 2,
Minute hand axis 1 in the axis or gear train 10 that rotates once per hour
6, and a lever 20 that turns on a contact member (not shown) when the engaging element 19 falls. The cam wheel 18 is provided with two sets of cam protrusions 22 facing each other, and an engaging element 19 that is in contact with the outer periphery of the cam wheel 18.
falls on the falling surface 24 twice in an hour, thereby outputting the signal TC at the hour and half past.

26 is a time code plate made of non-conductive material;
As shown in FIG. 3, it is attached to a shaft or hour hand shaft 28 within the wheel train 10 that rotates once every 12 hours.
The plane portion of the time code plate 26 is radially divided into 24 parts, and each radial area is further divided into 4 parts in the radial direction. This radial area is a time area TA ₁ to TA 1 representing the hour, that is, the time of the hour digits.
TA ₁₂ and the half hour area HTA ₁ to HTA ₁₂ representing half an hour
is arranged alternately, and the time domain
At TA ₁ to _{TA 12} , conductive portions 30 shown in black in the figure are appropriately provided in the radial region to represent the respective time codes. All of the conductive parts 30 are connected to a conductive part 32 near the center of the time code plate 26, and are further grounded. On the other hand, the half-hour regions HTA ₁ to HTA ₁₂ are not provided with any conductive portions and are comprised only of non-conductive portions. The time code plate 26 is in contact with contacts 34 to 40 corresponding to each divided area in the radial direction within the radial area, and the level is H level when it comes into contact with a non-conductive part, and the level is L level when it comes into contact with a conductive part. It outputs a signal of
In particular, the output signals CD ₁ to _{CD 4} are all set to be at H level at half o'clock.
Incidentally, the time code signal from this time code plate 26
CD ₁ to _{CD 4} are set to be switched and output before the hour actually reaches the hour or half-hour.

Reference numeral 42 denotes a time signal control circuit, which inputs the signal TC etc. from the time signal contact 14 and outputs various control signals.

Reference numeral 44 denotes an hour/half hour discrimination circuit which inputs the code signal from the time code plate 26 and outputs an hour/half hour discrimination signal HS.

46 is a time code storage circuit that stores a time code, and stores the time code signal supplied from the hour/half hour discrimination circuit 44 by inputting read signals RD ₂ and RD ₃ from the time signal control circuit 42. It is something to do.

Reference numeral 48 denotes a morning/afternoon discrimination circuit, which discriminates between morning and afternoon based on the change in the current time code and the previous time code stored in the time code storage circuit 46.

50 is a stroke number control circuit, which outputs a pulse signal STEND to stop striking in accordance with the time code stored in the time code storage circuit 46;
In response to the signal HHLG from the time control circuit 42, it also instructs the number of half-hour strokes.

Reference numeral 52 denotes a nighttime noise reduction circuit, which inputs signals from the time code storage circuit 46 and the morning/afternoon discrimination circuit 48 and stops the time alarm at a predetermined time; This is to cancel the .

Reference numeral 54 denotes a sound generation operation control circuit, which starts the sound generation operation by inputting the signal HRS from the time signal control circuit 42, and prohibits the generation of the half-hour melody sound by the signal HHLG. A signal MEMODE indicating the start of the striking operation and a signal STMODE indicating the start of the striking operation are output.

Reference numeral 56 denotes a time signal sound generation circuit, which generates a time signal sound in response to the signals MEMODE and STMODE from the sound generation operation control circuit 54. At night, the sound is generated by the signal NIG from the night silencer circuit 52. It is intended to stop.

58 is a monitor switch; 60 is a monitor operation start signal in response to the operation of the monitor switch 58;
The MST is applied to the sound generation operation control circuit 54 for monitoring operation.

Reference numeral 61 denotes an initial reset circuit for initially resetting each circuit when a battery is inserted.

Next, the configuration and operation of each circuit will be explained using a detailed circuit diagram of each circuit shown in FIG.

FIG. 4 shows the time signal control circuit 42, hour/half hour discrimination circuit 44, and time code storage circuit 4 shown in FIG.
6. AM/PM discrimination circuit 48, night silence circuit 52
FIG.

The time signal control circuit 42 shown in the figure includes a bounce delay circuit 62 that delays the signal TC from the time signal contact 14 for a certain period of time to prevent chattering, and each output terminal Q.
Flip-flops 6 are connected in series from to input terminal D and input a 32Hz signal to each clock input φ.
4 to 70, the output signals A ₃ and ₄ of the flip-flops 68 and 70, and a NAND gate 72 that receives the 32 Hz signal and outputs the signal HRS for starting the time reporting operation, and the output signals of the flip-flops 64 and 66.
An OR gate 74 that inputs A ₁ and A ₂ , and an OR gate 78 that inputs its output signal A ₅ and the 32Hz signal inverted by the inverter 76 and outputs a signal RD ₁ .
and the output signals ₂ of flip-flops 66 and 68,
NOR gate 80 inputting _A3 and its output signal
A NAND gate 82 inputs RD ₃ and the signal HS from the hour/half hour discrimination circuit 44, an AND gate 84 inputs the signal HS and the signal MONR from the monitor control circuit 60, and the output signal is inverted by the inverter 86. and an OR gate 88 which inputs the signal MONR and outputs the signal HHLG.

The hour/half hour discrimination circuit 44 inputs the code signals CD ₁ to _{CD 4} from the time code plate 26 _shown in FIG. Flip-flops 90 to 96 input to input φ and their output signals B ₁ to _{B 4}
and a NAND gate 98 which inputs and outputs a signal HS for determining whether it is on the hour or half an hour.

The time code storage circuit 46 inputs the output signals B ₁ to B ₄ of the hour/half hour discrimination circuit 44 to input terminals D, and inputs the read signal RD ₂ from the time signal control circuit 42 to a clock input φ. flip-flops 100 to 106 and their respective output signals C ₁ to _{C 4}
is input to the input terminal D, and the read signal _RD3 from the time information control circuit 42 is input to the clock input φ.

The AM/PM discrimination circuit 48 includes a NAND gate 118 which inverts and inputs the output signals C ₃ and C ₄ of the time code storage circuit 46, and a NAND gate 118 which inverts and inputs the signal C ₁ and inputs the signals C ₂ , C ₃ and C _{4 .} Nand gate 1 to input
20, a NAND gate 122 into which signals H ₃ and H ₄ are inverted and inputted, and a NAND gate 124 into which signal H ₁ is inverted and inputted and signals H ₂ , H ₃ and H ₄ are inputted.
and a NOR gate 126 inputting signals D ₂ and D ₃ .
NOR gate 128 inputting signals D ₁ and D ₄ and NOR gate 1 inputting their output signals D ₅ and D ₆
30, and a flip-flop 134 which inputs its output signal D ₇ to a clock input φ and further inverts the signal D ₇ by an inverter 132 and inputs it to the clock input. The nighttime muffling circuit 52 receives the output signal H ₁ of the time code storage circuit 46.
The first decoder 136 inputs ~ _H4 and detects 1 o'clock to 5 o'clock, and the second decoder 136 detects 11 o'clock and 12 o'clock.
A decoder 138 and AND gates 140 and 142 which input these output signals E ₁ and E ₂ to one input terminal, respectively, and input output signals AMS and PMS of the AM/PM discrimination circuit 48 to other input terminals, respectively.
And input these output signals to create a night silence signal.
It is composed of an OR gate 144 that outputs NIG.

The operation of each circuit having the above configuration will be explained based on the time charts shown in FIGS. 5 to 7.

First, the operation of the time signal control circuit 42 will be explained using the time chart shown in FIG.

As shown in FIG. 5, when the time signal contact 14 is turned on, the signal TC becomes H level. this signal
TC is delayed for a certain period of time by the bounce delay circuit 62 and output as a signal BDS. When this signal BDS becomes H level, the output _A1 of the flip-flop 64, which has been reset in advance by the signal CLS from the initial reset circuit 61, switches to H level in synchronization with the falling edge of the 32Hz signal.
The output signals A ₂ , A ₃ , and ₄ of the flip-flops 66, 68, and 70 are also sequentially switched to H, H, and L levels.

Therefore, the output signal _A5 of the OR gate 74 inputting signals ₁ and _A2 becomes L level for one cycle of the 32Hz signal, and the output signal A5, which is inverted with this signal _A5 ,
Output signal RD ₁ of OR gate 78 which inputs Hz signal
becomes L level for one pulse of the 32Hz signal. Then, the output signal RD ₃ of the NOR gate 80 which inputs the signals ₂ and A ₃ goes to the H level for one cycle of the 32Hz signal following the signal RD ₁ , and the output signal HS of the hour/half hour discrimination circuit 44 to be described later becomes If it rises to H level, the output signal RD ₂ of the NAND gate 82
becomes the inverted signal of signal _RD3 .

On the other hand, the output signal HRS of the NAND gate 72 is
When the input signals A ₃ and ₄ and the 32Hz signal all go to H level, it falls to L level, and when the output of flip-flop 70 is switched, it rises to H level. This change activates a sound generation operation control circuit 54, which will be described later.

When the signal HS goes to H level, indicating that it is on the hour, the normally open AND gate 84
The output of HHLG also becomes H level through the OR gate 88, and the sound generation operation control circuit 54 is instructed to generate a melody. In the case of half o'clock, when the signal RD ₁ goes to L level, the hour/half hour discrimination circuit 44, which will be described later, determines that it is half o'clock and sets the signal HS to L level. 82 output signals
_RD2 is kept at H level to prevent time reading.

In this way, the time signal control circuit 42 controls the signal TC to be H.
When the level is reached, a signal RD ₁ is generated to start determining whether it is on the hour or half-hour, a read signal RD ₂ is generated to read the current time, a read signal RD ₃ is generated to update the memorized time, and a sound generation operation is generated. The signal HRS for starting the process is sequentially output.

Next, using the time chart shown in FIG. 6, the hour/half hour discrimination circuit 44 and the time code storage circuit 46
Explain the operation.

The hour/half hour discrimination circuit 44 and the time code storage circuit 46 receive a signal from the initial reset circuit 61.
It is set to the initial state by CLS. That is, the flip-flops 90 to 90 of the hour/half hour discrimination circuit 44
96, reset the flip-flops 100 and 110 in the time code storage circuit 46, and reset the flip-flops 102 to 106 and 112 to 116.
and set it to the 1 o'clock state.

Thereafter, the time is set, and when the time signal contact 14 (FIG. 1) turns on on the hour, the output signal _RD1 of the time signal control circuit 42 described above falls to the L level.

In synchronization with the fall of this signal _RD1 , the flip-flops 90 to 96 in the hour/half hour discrimination circuit 44
switches the output state according to the states of the input signals CD ₁ to _{CD 4} . For example, if it is 5 o'clock now, the signals CD ₁ to _{CD 4} from the time code plate 26 (FIG. 3)
are at L, H, L, and H levels, respectively, so that the output signals B ₁ of flip-flops 90 to 96
~B ₄ also becomes L, H, L, H level. this signal
If there is even one signal at the L level, such as _B1 to _B4 , the output signal HS of the NAND gate 98 becomes the H level, thereby determining that it is the hour.

When the time advances to 5:30, the signals CD ₁ to _{CD 4} from the time code plate 26 all go to H level as described above, and when the signal RD ₁ goes to L level, the output signals B from flip-flops 90 to 96 ₁ ~ _B4
All become H level. Therefore, the output signal HS of the NAND gate 98 becomes L level, and it is determined that it is half o'clock.

On the other hand, when the hour comes, the time code storage circuit 46
The flip-flops 100 to 106 within the circuit switch in synchronization with the fall of the signal RD ₂ from the time control circuit 42 in response to the signals B ₁ to B ₄ from the hour/half hour discrimination circuit 44 immediately after switching. Switch its output.
In the case of FIG. 6, only the output signal _C3 of flip-flop 104 is switched to L level. next,
When the signal _RD3 goes to L level, the output states of the flip-flops 110-116 are switched in accordance with the output signals _C1 - _C4 of the flip-flops 100-106. In this way, flip-flop 100
106 and flip-flops 110 to 116 are provided, and it is this time code storage circuit 46 that shifts the reading timing of each time code.
This is because the AM/PM discrimination circuit 48 is configured to discriminate AM/PM from the current time and the previous time stored in the memory.

After that, at half o'clock, as mentioned above, it is on the hour.
The output signals _B1 to _B4 of the half-hour discrimination circuit 44 are all H.
become the level. At this time, the output signal _RD2 of the time signal control circuit 42 is maintained at H level, and the output states of the flip-flops 100-106 and 110-116 do not change.

Furthermore, when the hour comes on the hour again, the output signal HS of the hour/half hour discrimination circuit 44 becomes H level.
Since the signal RD ₂ output from the time control circuit 42 also falls to the L level, the flip-flops 100 to 1
The output state of the flip-flops 110-11 changes according to the states of the input signals _B1 - _B4 , and subsequently, when the signal _RD3 goes to L level, the output state of the flip-flops 110-11 changes.
The output state of 6 is also switched.

In this way, the hour/half hour discrimination circuit 44
The determination is made every half hour to change the state of the determination signal HS, and the time code storage circuit 46 stores the code signal of the current time in synchronization with the falling edge of the signals RD ₂ and RD ₃ that are output on the hour. It is read and memorized.

Next, the operations of the morning/afternoon discriminating circuit 48 and the nighttime silencing circuit 52 will be explained using the time chart shown in FIG.

NAND gate 118 of AM/PM discrimination circuit 48
124 respectively input predetermined signals from the time code storage circuit 46 as described above, and NAND gates 118 and 122 output signals D ₁ and D ₃ which become L level when a signal indicating 12 o'clock is input. , and when the NAND gates 120 and 124 receive a signal indicating 1 o'clock, they output signals D ₂ and D ₄ that become L level. Therefore, as described above, when the time code storage circuit 46 is set to 1 o'clock in the initial state by the initial reset circuit 61, the NAND gate 12
Signals D ₂ and D ₄ of 0 and 124 become L level. At this time, the flip-flop 134 has also been initialized, and the morning signal AMS goes to H level.
In the initial state, 1:00 AM will be set. In this initial state, for example, pointer display 1
2 (Fig. 1) and sets it to 12 o'clock, the output signal of the time code storage circuit 46 as described above.
C ₁ to C ₄ enter a state indicating 12 o'clock in synchronization with the fall of signal RD ₂ . Therefore, the signal _D2 becomes H level, and in its place, the signal _D1 becomes L level.

At this time, since the output signals H ₁ to H ₄ of the time code storage circuit 46 still indicate 1 o'clock, the signal D ₄ remains at the L level. For this reason,
The output signal D ₆ of the NOR gate 128 inputting the signals D ₁ to D ₄ rises to H level, and the output signals _{H 1 to H 4} of the time code storage circuit 46 become in a state indicating 1 o'clock due to the fall of the signal RD 3. Signal D ₄ is H
Therefore, this signal _D6 becomes L level.

When the time is changed from 1 o'clock to 12 o'clock in this way, a pulse is generated in the signal D ₆ , and the output signal D ₇ of the NOR gate 130 goes low at the rise of this pulse.
become the level. The flip-flop 134 switches its output state in synchronization with the fall of the signal _D7 , and the signals AMS and PMS become L and H levels, respectively.

Thereafter, when the time reaches 1 a.m., the output signals C ₁ to _{C 4} of the time code storage circuit 46 switch to the state indicating 1 o'clock, the output signal D ₂ of the NOR gate 120 becomes L level again, and the signal D ₁ becomes Becomes H level. At this time, the output signals H ₁ to _{H 4} of the time code storage circuit 46 still indicate 12 o'clock, so
The output signal _D3 of the NOR gate 122 remains at the L level until this state is switched by the signal _RD3 .

Therefore, the output signal of NOR gate 126 is now
A pulse is generated at _D5 , and the output signal _D7 of the NOR gate 130 becomes L level at the rising edge of this pulse, and the flip-flop 134 switches its output state again in synchronization with the falling edge of the signal _D7 .

In this way, the morning/afternoon discrimination circuit 48 inputs each code signal of the current time and the previous time stored in the time code storage circuit 46, and inputs the code signals from 12:00 to 1:00,
Or when the time changes from 1:00 to 12:00,
It changes the afternoon.

On the other hand, the first decoder 136 of the nighttime noise reduction circuit 52
When detecting time code signals 1 to 5 of time code signals H ₁ to _{H 4} , the signal E ₁ is set to H level, and the second decoder 138 detects time code signals 11 and 12 of time code signals H ₁ to _{H 4} .
When detected, the signal _E2 is set to H level.

AND gate 14 in this nighttime silencing circuit 52
0 and 142 input signals AMS and PMS, respectively, and the AND gate 140 is open in the morning, and the AND gate 142 is open in the afternoon.
Therefore, if signals E ₁ and E ₂ are applied to the AND gates 140 and 142, respectively, the AND gate 1
The output of AND gate 142 is at H level from 1 a.m. to less than 6 p.m., and the output of AND gate 142 is at H level from 11 p.m. to less than 1 a.m. For this reason,
The output signal NIG of the OR gate 144 inputting the outputs of the AND gates 140 and 142 is 11 p.m.
to 6 a.m. until below 6 a.m.

FIG. 8 is a detailed circuit diagram of the number of strokes control circuit 50, sound generation operation control circuit 54, and monitor control circuit 60 shown in FIG.

The number-of-bats control circuit 50 receives a timing signal for batting.
A counter 146 that counts the number of strokes by inputting STCLK and its output signals J ₁ to J ₄ are each input to one input terminal, and inverters 148 to 1 are input to the other input terminals.
Exclusive NOR gates 156 to 162 each input signals ₁ to ₄ from the time code storage circuit 46 inverted at 54, an AND gate 164 to which all these outputs are input, and an output signal _J1 of the counter 146 and a An AND gate 166 inputs an inverted version of the signal HHLG from the time control circuit 42, and a signal indicating the end of time striking by inputting output signals J ₅ and J ₆ of AND gates 164 and 166.
It consists of an OR gate 168 that outputs STEND.

The sound generation operation control circuit 54 is connected to the monitor control circuit 6
an AND gate 170 which inputs the signal MONR from 0 and an inverted version of the signal HRS from the time control circuit 42; an OR gate 172 which inputs its output signal _I1 and the signal MST from the monitor control circuit 60; A NAND gate 17 receives the output signal _I2 and the output signal HHLG of the time control circuit 42.
4, a flip-flop 176 to which the output signal I ₃ and the signal STMODE are input, an inverter 178 which inverts the output, and a set input S to which the signal I ₂ is input.
a flip-flop 180 which inputs the signal FIN to the reset input and outputs the signal CCGR.
, a NAND gate 182 to which the signal I ₂ and the inverted version of the signal HHLG are input, a flip-flop 186 to which the output signal I ₄ , the melody end signal MEEND, and the signal STEND inverted by the inverter 184 are input, and its output signal and an inverter 188 that inverts the output voltage.

The monitor control circuit 60 includes the monitor switch 5
an AND gate 190 that inputs the signal MS from 8 and the signal CCGR from the sound generation operation control circuit 54;
One-shot multivibrators 192 and 194 input the output signal and the signal CCGR, respectively.
and a delay circuit 196 that inputs the output signal _G1 .
and a flip-flop 198 which inputs signals G ₁ and G ₂ to set input S and reset input R, respectively.

Next, the operation of each circuit having the above configuration will be explained using the time chart shown in FIG.

When the hour reaches the hour and the time signal starts, the output signal HRS of the time signal control circuit 42 remains at L level for a certain period of time.
A pulse is generated in the output signal I ₁ of the AND gate 170 of the sound generation operation control circuit 54 . This pulse generated in signal I ₁ is generated in signal I ₂ via OR gate 172 . Due to the pulse generated in this signal I ₂ ,
Flip-flop 180 is set and its output signal CCGR goes to L level, making it in a sound generating state.

Further, when the signal I ₂ becomes H level, the output signal I ₃ of the NAND gate 174 becomes L level, and in synchronization with this fall, the output state of the flip-flop 176 is switched and the signal MEMODE becomes L level. When this signal MEMODE goes to L level, a melody sound generation state is entered and a predetermined melody is generated.

When the melody ends, the melody end signal MEEND output by the time signal generation circuit 56 goes to L level, and the output state of the flip-flop 186 changes and the signal STMODE goes to L level. The output state of is switched and the signal MEMODE goes to H level, and the ticking sound is generated.

When this signal STMODE becomes L level, the reset state of the counter 146 in the number of strokes control circuit 50 is released and the number of pulses generated in the signal STCLK is counted.

For example, if the time is 3 o'clock, when the counter 146 counts "3", the AND gate 164
The output signal _J5 becomes H level, and the OR gate 16
8, the time signal end signal STEND becomes H level. As a result, the flip-flop 186 switches its output state, and the signal STMODE becomes H level again, resetting the counter 146, and then the signal FIN output from the alarm sound generation circuit 56.
As a result, the flip-flop 180 is reset and the timing operation is completed.

Furthermore, at half o'clock, the signal HHLG from the time control circuit 42 goes to the L level, so even if a pulse occurs in the signal _I2 , the signal _I3 remains at the H level. Therefore, the signal MEMODE is also kept at the H level and no melody sound is generated. However, the output signal I ₄ of the NAND gate 182 goes to L level with the rise of signal I ₂ , and in synchronization with this fall, the flip-flop 186 switches its output state, and the signal STMODE goes to L level, causing the ticking sound to occur. become.

Then, the counter 146 operates again, but this time the AND gate 166 is in the open state, so when the counter 146 counts "1", its output signal J ₆ becomes H level, and the OR gate 16
The signal STEND also becomes H level via the signal STEND.

Therefore, the output state of the flip-flop 186 is switched, and the half-hour time signal ends with only one ticking sound being generated.

Meanwhile, the monitor switch 58 is operated and the signal is
When a pulse is generated in the MS, a pulse is generated at the output of the AND gate 190, which is open except when the time is reported, and the pulse is output from the one-shot multivibrator 192.

This pulse generated in the signal _G1 causes the flip-flop 198 to enter the set state, and the signal
MONR goes to L level and becomes a monitor state.
After that, the pulse generated in signal G ₁ is transmitted to delay circuit 1
96 output signal MST, the OR gate 17
2 output signal I ₂ is generated. Thereafter, the above-described operation generates a melody sound and a ticking sound, and when the flip-flop 180 is reset by the signal FIN and its output signal CCGR becomes H level, the one-shot multivibrator 194
A pulse is output from the flip-flop 198
is reset and the monitor state is released.

In the case of this embodiment, even if the output signal of the time code plate 26 has already reached the next time, the states of the signals H ₁ to _{H 4} from the time code storage circuit 46 do not change until the hour reaches the hour. Even if a monitor operation is performed during this time, the next time will not be reported.

FIG. 10 is a block diagram showing the circuit configuration of the time signal generating circuit 56 shown in FIG. 1, and FIG. 11 is a timing chart thereof.

The time signal generation circuit 56 includes a first melody code generation circuit 200, a second melody code generation circuit 202, variable frequency dividing circuits 204, 206, a timing signal generation circuit 208, and a sound generation circuit 210.

When the sound generation state occurs and the signal CCGR goes to L level, the timing signal generation circuit 208 and the variable frequency dividing circuit 2
04, 206 is activated, and the timing signal generation circuit 208 outputs the timing signal MECLK.
1. MECLK2 is output.

At this time, when the signal MEMODE goes to L level, the code signal of each melody is outputted from one or both of the first melody code generation circuit 200 and the second melody code generation circuit 202, and the variable frequency dividing circuits 204 and 206 are outputted as appropriate. supplied to

The sound generation circuit 210 responds to the frequency signals F ₁ and F ₂ output from the variable frequency dividing circuits 204 and 206.
A melody emanates from it.

On the other hand, for the ticking sound, when the signal STMODE goes to L level, a pulse is generated in the signal STCLK output from the timing signal generation circuit 208, and as a result, the sounding circuit 210 generates the ticking sound.

Incidentally, when the sound is muted at night, the signal NIG applied to the sound generation circuit 210 becomes H level, and the sound generation operation is blocked.

Furthermore, when the melody ends, the signal MEEND is output from the second melody code generation circuit 202.
Once becomes L level and furthermore, when the timing is completed, the output signal of the timing signal generation circuit 208
A pulse is generated on FIN to indicate to each of the other circuits that their respective operations are complete.

As detailed above, in the present invention, a specific code indicating half o'clock is formed on the time code board, and when this specific code is detected, it is determined that it is half o'clock, and a notification for half o'clock is sent. It is something that generates a sound.

(f) Effects of the invention According to the invention, it is possible to accurately distinguish and print the hour and half o'clock even immediately after the battery is inserted, and it is possible to prevent false alarms.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.
Figure 2 is a diagram showing the detailed structure of the time signal contact shown in Figure 1, Figure 3 is a diagram showing the detailed structure of the time code plate shown in Figure 1, and Figure 4 is a diagram showing the detailed structure of the time code plate shown in Figure 1. A circuit diagram showing the detailed structure of the hour control circuit, the hour/half hour discrimination circuit, the time code storage circuit, the morning/afternoon discrimination circuit, and the night silence circuit, Figures 5 to 7 are the time charts of Figure 4, Figure 8 is a circuit diagram showing the detailed configuration of the number of strokes control circuit, sound generation operation control circuit, and monitor control circuit shown in Figure 1, Figure 9 is the time chart of Figure 8, and Figure 10 is shown in Figure 1. A block diagram showing the detailed configuration of the time signal generation circuit, FIG.
This is a time chart of Figure 0. 2... Oscillation circuit, 4... Frequency dividing circuit, 6... Waveform shaping circuit, 8... Motor, 10... Wheel train, 12...
... Pointer display, 14 ... Time signal contact, 26 ... Time code plate, 42 ... Time signal control circuit, 44 ... On the hour.
Half-hour discrimination circuit, 46...Time code storage circuit, 4
8...AM/PM discrimination circuit, 50...Number of strokes control circuit, 52...Night silence circuit, 54...Sound generation operation control circuit, 56...Time signal sound generation circuit, 58...Monitor switch, 60...Monitor control circuit.

Claims (1)

[Claims for Utility Model Registration] It has a time signal circuit that displays the time in the form of hand movement and generates different types of time signal sounds for the hour and half-hour based on the hour-hour discrimination signal and the half-hour discrimination signal. In a watch, a time signal contact mechanism that generates a time signal start signal that starts the operation of the time signal circuit every 30 minutes on the hour and half past, a time code of the hour digit corresponding to the hand time and all the respective times. A time code plate in which a specific code different from each time code is formed between the codes, and a half-hour discrimination signal is detected when a specific code is detected from the time code plate based on the time signal start signal, and a specific code is detected. A time-reporting electronic timepiece characterized by being provided with an hour/half-hour discrimination circuit that outputs an hour-hour discrimination signal when the hour is on the hour.