JPH02126494A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To simplify a refreshing method and to hold storage even when a power failure occurs by executing refreshing under the standby state of a row address strobe without using an external cycle. CONSTITUTION:When the 'H' state of the row address strobe, the inverse of RAS continues for the period of a delay circuit 2, an oscillation circuit 1 is activated and generates a clock pulse. Further, this clock pulse works as the trigger pulse of a counter circuit 3 and executes increment for a row address for which refreshing and rewriting is to be executed. On the other hand, the cycle of the inverse of RAS in an interval part is started, and the series of refreshing is executed. Thus, the refreshing method can be simplified, and the storage can be held when the power failure occurs by executing the refreshing under the standby state of the row address strobe without using the external cycle.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a refresh method for a dynamic semiconductor memory device.

[Conventional technology]

Conventionally, dynamic semiconductor memory devices (hereinafter referred to as "dynamic semiconductor memory devices")

(DRAM) is refreshed using a primary operation. An example of its operation will be explained using FIG.

In Figure 2, 1 is a memory cell capacitor (hereinafter referred to as C8), 2 is a sense amplifier, and 3 is a bit line (hereinafter referred to as BL).
, 4 is a word line (hereinafter referred to as WL), and 5 is a write line.
This is a read transistor.

First, C8 is volatile, so over time C3
The accumulated charge of will disappear. Therefore, WL (4) is activated and gate (5) is opened. Then, the potentials of BL and BL begin to change slightly. It is amplified by the sense amplifier (2) and returned to C8 to close WL. This is a refresh operation, and examples of this refresh method include RAS only refresh, CAS before RA
There are S refresh, hidden refresh, etc.

[Problem to be solved by the invention]

All conventional refresh methods require an external clock including a row address strobe. This makes clock control complicated in applications. Furthermore, in the event of a power outage, memory cannot be retained.

This invention was made in order to solve the above-mentioned problems, and it simplifies the refresh method and makes it possible to maintain memory during a power outage.

[Means for Solving the Problems] A method for refreshing a semiconductor memory device according to the present invention includes:
The row address strobe is in a standby state so that refreshing can be performed without using an external cycle.

[Effect]

According to the refresh method of a semiconductor memory device according to the present invention, even if the row address strobe remains in a standby state, refresh can be performed by generating an internal row address strobe.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, when the H state of the row address strobe (hereinafter referred to as RAS) continues for a period of delay circuit 2, oscillation circuit 1 is activated and generates a clock pulse. This clock pulse acts as a pulse for the counter circuit 3, and increments the row address for refreshing and rewriting. Meanwhile, the internal RAS cycle begins and a series of refreshes are performed. The timing diagram at this time is number 31! S! 1(a), and its operation will be explained. First, when the internal RAS falls, the word line rises, the sense clock is activated, and the potential of the memory cell is rewritten to a completely high level (low level). Here, a problem arises when external RAS comes in during the refresh cycle using this internal RAS signal. In the example in Figure 1, (1) the external RAS enters before the rise of WL, and 12) the external RAS enters before the rise of WL.
Let's consider separately the case where someone stands up and enters.

The case of (1) is shown in Figure 3 (b), and the case of (2) is shown in Figure 3 (
Explain using C). First, in case (1), since the information in the memory cell is not transmitted to the BL via the transfer gate, priority is given to the external RAS, and from the falling edge of the external RAS, the internal RAS is activated and refreshed. In the case of (2), the internal RAS is turned down after waiting for the sense clock generated by the internal RAS to enter the standby state. In this way, refresh can be performed while the RAS is in standby mode without depending on the external RAS cycle.

Next, regarding memory retention in the event of a power outage, this can be achieved by backing up the memory using, for example, an internal power source.

〔Effect of the invention〕

As described above, according to the present invention, refresh can be performed by internal RAS even when RAS is in standby state, so RAS-only refresh, etc.
There is no need to use external pulses as in CAS before RAS refresh, and the refresh method can be simplified. Also.

As long as it is backed up with an internal power supply, it can retain its memory even in the event of a power outage.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a configuration diagram of memory cells and sense amplifiers, FIG. 3(a) is a timing diagram of refresh operation, and FIG. 3(b) is an external R.A.
Figure 3 (C) is a timing diagram of the refresh operation when S enters before the falling edge of WL.
shows a timing diagram of a refresh operation when WL rises and enters. Further, 1 in Fig. 1 is an oscillation circuit, 2 is a delay circuit, 3 is a counter circuit, 1 in Fig. 2 is a memory cell capacitor, 2 is a sense amplifier, 3 is BL, 4 is WL, and 5 is a writing/reading transistor. BL is a bit line, WL is a word line, RAS is a row address strobe, extRAS is an external row address strobe, 1ntRAs is an internal row address strobe, and SO is a sense clock. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] A dynamic semiconductor memory device characterized in that a refresh operation can be performed while a row address strobe is in a standby state.