JPH0212670A - Pll circuit - Google Patents

Abstract

PURPOSE:To attain setting while varying a phase lock range respectively by applying phase locking of the PLL circuit while each bias voltage is set to an optimum bias value. CONSTITUTION:Plural magnetic heads are switched and a changeover switch 8 controlled by a magnetic head switching signal generating circuit 10 is switched synchronously with respect to a reproduction signal inputted from the magnetic heads. A control voltage of a different voltage controlled oscillator VCO 5 is held in a sample-and-hold circuit 9 in matching with plural different reproducing signals via the changeover switch 8. The sample-and-hold output voltage as a bias voltage of a low pass filter LPF 4 of the PLL circuit 2 is biased in matching with the phase lock of the different reproducing signal. Thus, the phase lock range is varied in response to each input signal to attain stable phase lock operation.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to a PLL circuit that extracts a synchronous clock signal from a reproduced signal, and is particularly suitable for a PLL circuit that extracts a synchronized clock signal from a plurality of rotary magnetic heads. The present invention relates to a PLL circuit that extracts a synchronous clock signal.

(B) Prior Art Conventionally, a PLL circuit as shown in the block diagram of FIG. 3 has been provided as a PLL circuit for extracting a reproduced clock signal in variable speed reproduction of a magnetic recording/reproducing device having a plurality of rotary magnetic heads. It had been.

In the figure, 1 is an input terminal to which a reproduction signal recorded on a recording medium is amplified by a reproduction head amplifier (not shown), and 2 is a PLL circuit, a phase comparison circuit, a low-pass filter (hereinafter referred to as LPF), and a voltage Controlled oscillation circuit (hereinafter referred to as V
(referred to as CO). 3 is a phase comparison circuit that compares the phase of the clock signal in the input reproduction signal and the output signal of the VCO, 4 is an LPF for removing high frequency components and noise, and 5 is a VCO 16 that oscillates under voltage control.
The output terminal 7 of the LL circuit 2 is a bias circuit connected to the input side of the LPF 4.

Reproduction signals from a plurality of magnetic heads applied to the input terminal 1 are supplied to a phase comparator circuit 3. On the other hand, this phase comparator circuit 3 receives the output signal of vcos, which is the output signal of the 20 PLL circuit 2, at $! It has been added back.

In the phase comparator circuit 3, the clock signal in the reproduced signal and the VC
A phase comparison of the O5 launch signal is performed, and the compared phase difference is detected and output.

This phase difference signal is supplied to the LPF 4, which removes unnecessary high frequency components and noise, and has a lock holding function for the PLL circuit 2 by the filter's capacitor. This LPF 4 is biased by the bias circuit 7, and
It controls the output voltage of PF4.

The phase difference signal passes through the LPF 4 and is applied to the VCO 5 as a correction signal voltage of the excavation frequency, and the VCO 5 is voltage-controlled by the correction signal voltage and frequency-controlled to match the clock signal of the reproduction signal.

The frequency control of the VCO 5 ultimately oscillates a synchronized clock signal 3J+ accurately synchronized with the clock signal of the reproduced signal at the lock-up time, and outputs it to the output terminal 6.

In this way, the oscillation frequency of the VCO 5 can be precisely synchronized with the input reproduction signal by the phase locking effect of the PLL circuit 2.

The phase lock operation of the PLL circuit 2 can widen the lock range and further shorten the lock up time (response time) by using the bias voltage of the bias circuit 7 of the LPF 4.

(c) Problems to be Solved by the Invention Using a rotating magnetic head, the windings of 90 mm are placed on a magnetic tape wound around a cylinder at an angle, and have different azimuth angles with respect to the head scanning direction and are opposed to each other. In a magnetic recording and reproducing device that records and reproduces data using magnetic heads placed at different positions, when performing variable speed reproduction, the two magnetic heads must reproduce No. 13 recorded on the magnetic tape at different relative speeds. .

In this way, the clock signals that must be reproduced at different relative speeds from the two electrical heads will each have different frequencies.

Using these clock signals of different frequencies as input signals,
In order to perform phase lock operation in a conventional PLL circuit and generate a synchronous clock signal, the bias voltage of the bias circuit 7 of the LPF 4 must be set so that the phase lock is performed according to two different input frequencies. I have to.

This bias voltage is for the two different frequencies mentioned above.
The center value of the frequency difference was chosen to make it easier to phase-lock to each frequency.

Since the bias voltage of the LPF 4 is set to the center value of the same frequency difference in this way, a lock state is not achieved in each phase lock state.

The drawback was that the phase lock range became narrower, making it easier to mislock.

This invention has been made in view of the above points, and its purpose is to eliminate the drawbacks of the conventional example and to provide a phase lock range for a plurality of different input playback signals according to each input signal. It is an object of the present invention to provide a PLL circuit that can perform stable phase lock operation by changing the phase lock.

(d) Means for Solving the Problem The PLL circuit of the present invention detects a reproduced clock signal from a reproduced signal recorded on a recording medium of a magnetic recording/reproducing device equipped with a plurality of rotary electric heads. A head switching signal generation circuit that generates a switching signal in accordance with the switching timing of a plurality of rotary magnetic heads, a changeover switch that changes the VCO control voltage of the PLL circuit, and a voltage sampling/holding of the VCO control voltage of the PLL circuit. A sampling and holding circuit is provided, and the output voltage of the sampling and holding circuit is supplied to the bias circuit of the LPF of the PLL circuit.

(E) Operation A plurality of magnetic heads are switched, and the changeover switch controlled by the magnetic head switching A3 generation circuit is switched in synchronization with the reproduction signal inputted from the magnetic heads.

Different control voltages of the VCOs are held in the sampling and holding circuit via this changeover switch in accordance with the plurality of different reproduction signals.

This sampled and held output voltage is biased as a bias voltage of the LPF of the PLL circuit in accordance with the fender rotor operation of different reproduction signals.

In this way, the PLL circuit provides phase locking by applying the optimal side all voltages to the reproduced signals of different frequencies using the bias circuit.

(F) Embodiment An embodiment of the PLL circuit according to the present invention will be described based on the block diagram of FIG. 1 and the switching timing diagram of FIG. 2.

Note that the same parts as in the conventional example are given the same reference numerals, and the explanation thereof will be omitted.

In the figure, 8 is a switch that is switched by a head switching signal, 9 is a sampling and holding circuit that performs sampling and holding via the VCOS control voltage switch 8, and 10 is a head switching circuit that outputs playback signals by switching a plurality of magnetic heads. This is a head switching signal generation circuit.

When a magnetic tape recorded by a magnetic recording/reproducing device (not shown) having a plurality of rotary magnetic heads is reproduced by performing variable speed reproduction in accordance with the magnetic heads, each reproduction signal is sent to the input terminal of the PLL circuit 2. Added to 1. PLL
The circuit 2 extracts a clock signal from each of the different reproduction numbers 13, phase-locks a synchronous clock signal synchronized with each different clock signal, finds it, and outputs it from an output terminal 6.

As described above, the reproduced signals supplied to the input terminal 1 have different frequencies because they are reproduced by variable speed reproduction.

At this time, the control voltage of the VCO 5 is a QM control voltage of different values depending on the synchronized clock signal phase-locked to the clock signal of each different input reproduction signal.

Now, an example will be described in which the plurality of magnetic heads are two heads, A head and B head. A.

The control voltages of the VCO 5 which are phase-locked to the clock signals of the different reproduction signals from the B head are sampled and held in the sampling and holding circuit 9 via the switches 8, respectively.

Figure 2 shows the switching pulses (hereinafter SW) of heads A and B.
FIG. 2 is a timing diagram showing the RF window (hereinafter referred to as RFW) signal.

FIG. 2(a) is a timing diagram showing the RF multiplied signal reproduced by the A head and the RF multiplied signal reproduced by the B head.
Figure (b) shows the switching SWP of the A and B heads. This SWP is "L" when the A head is being reproduced, and is "H" when the B head is being reproduced. Also, RFW in FIG. 2 (C) is a timing signal that becomes "L" during the period when the reproduction signal exists. It is.

Now, at point m, when the A head is taking in the reproduced signal and supplying this reproduced signal to the input terminal 1 of the PLL circuit 2, the VCO 5 is a synchronized clock signal that is phase-locked to the A head reproduced clock ε. The control voltage at this time is supplied to the sampling hold circuit 9 via the switch 8.

Switch 51 of switch 8 is connected to contact C, and the above control voltage is held in capacitor C1 of sampling hold circuit 9. The S2 switch is connected to the C contact, and the sampling hold circuit 9 performs sampling and holding.
The output signal is supplied to the bias circuit 7 via the S2 switch, and sets the bias voltage of the LPF 4.

When the reproduction signal of the A head disappears and the RFW waveform becomes "H" after progressing to point 1 from point m in FIG.
2 switch switches to C contact.

The capacitor C2 of the sampling hold circuit 9 is charged with a control voltage value optimal for B head reproduction No. 3. This charged DC voltage is supplied to the bias circuit 7 and becomes a bias voltage for the LPF 4.

Progressing from point 0 to point 1 in Figure 2, the B head reproduction signal is extracted, the SWP waveform becomes "H", and the RFW waveform becomes "L" again.
'', the S1 switch of the switch 8 switches to the b contact, and the control voltage of the VCO 5 phase-locked to the clock signal of the B head reproduction signal charges the capacitor C2 of the sampling hold circuit 9 via the S1 switch.

This capacitor C2 has previously been charged with a voltage optimal for the phase lock operation of the B head reproduction signal, but it is corrected again by the operation of the PLL circuit 2, and a more normal voltage is held.

This optimal control voltage is supplied to the bias circuit 7 via the S2 switch, and sets the bias voltage of the LPF 4.

In this way, the timing of the head switching signal generation circuit 1O synchronized with the switching timing of the magnetic head is controlled, and when the A head is reproduced, the optimum bias for phase locking to the clock signal of the A head reproduction signal is set by the PLL.
The synchronized clock signal can be applied to the LPF 4 of the circuit 2 to perform phase lock operation under optimal conditions, and the VCO 5 can oscillate and output a synchronized clock signal.

Also, when switching to the B head, in accordance with this switching timing, an optimum control voltage different from that used during reproduction of the A head is supplied from the sampling hold circuit 9 to the bias circuit 7, and the bias voltage of the LPF 4 of the PLL circuit 2 is set. ,
The synchronized clock signal phase-locked to the B head reproduction clock signal is transferred to the VC by optimal phase-lock operation.
O5 can oscillate and output.

In this way, even when the synchronous clock frequencies corresponding to each magnetic head are different, the bias voltage of LPF4 is set to the optimum phase lock value for each synchronous clock frequency, widening the phase lock range and achieving stable PLL.
The operation of circuit 2 is possible.

(G) Effects of the Invention According to the PLL circuit according to the present invention, even if the clock frequency of the reproduced signal being reproduced by a plurality of rotating magnetic heads differs depending on the magnetic heads, the PLL circuit can Since the phase lock operation is performed by setting the bias voltages for the phase lock operation of the PLL circuit to the optimum bias values in accordance with the switching timing of the magnetic head, each phase lock range can be set differently. Furthermore, this phase lock range is widened, and there is an effect that stable phase lock operation without mislock can be performed.

Moreover, it has excellent features such as being simple to configure and easy to implement.

[Brief explanation of the drawing]

1 and 2 show an embodiment of the PLL circuit according to the present invention, FIG. 1 is a block diagram, FIG. 2 is a timing diagram showing switching timing of A and B heads, and FIG. 2(b) is the SWP waveform, and FIG. 2(c) is the RFW waveform. FIG. 3 is a block diagram of a conventional PLL circuit. Explanation of main numbers 2: PLL circuit 3: Phase comparison circuit 4: Low pass filter (LPF) 5: Voltage controlled oscillator circuit (VCO) 7: Bias circuit 8: Switch circuit 9: Sampling hold circuit 10: Head switching signal generation circuit Patent applicant Kenwood Corporation

Claims (1)

[Claims] In a PLL circuit that detects a reproduced clock signal from a reproduced signal recorded on a recording medium of a magnetic recording/reproducing device equipped with a plurality of rotary magnetic heads, the switching timing of the plurality of rotary magnetic heads is determined. A head switching signal generation circuit that also generates a switching signal, a changeover switch that switches the VCO control voltage of the PLL circuit, and a sampling and holding circuit that samples and holds this VCO control voltage are provided, and the output voltage of this sampling and holding circuit is P
A PLL circuit characterized in that it is configured to supply a signal to a bias circuit of an LPF of an LL circuit.