JPH0212694A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce precharge power consumption and to decrease the transient current by applying less precharge to each bit line and applying precharge from a precharge power supply to a selected bit line via an output line and a selection MOS transistor (TR) in addition to the less precharge. CONSTITUTION:A reduction means 21 reducing the precharge is formed to a precharge device applying a precharge voltage simultaneously to bit lines B1-B4 and the reduction means applies less precharge to each bit line. On the other hand, a precharge power supply Vcc is connected to an output line 8 for the data transfer used in common by each bit line selected alternatively by a selection MOS TR 7 via a 2nd precharge MOS TR 22. Only the bit line selected via one selection MOS TR 7 selected alternatively by the power supply is precharged. Thus, the precharge power consumption is reduced and the transient current at precharge and discharge is reduced.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a semiconductor memory device of a dynamic operation type having a MOS transistor configuration, and more specifically relates to a bit line precharge mechanism of the semiconductor memory device, and relates to reduction of power consumption for precharge, precharge and discharge. For the purpose of reducing transient current during
A precharging mechanism is provided that precharges each of the P1- transistors by making all of the P1 transistors conductive all at once, and each P1 transistor connected to each bit line across the precharging MO3I transistor and the bit line is provided. In a semiconductor memory device that selectively turns on transistors MOS 1 for selection to select one of the bit lines and outputs data to an output line shared by each bit line, the precharge mechanism A reducing means for reducing the amount of precharge to the line is formed, and a precharge power source is connected to the output line via a second precharge MOS transistor.

[Industrial Application Field] The present invention relates to a dynamic operation type semiconductor memory t'3 device having a MOS transistor configuration, and more particularly to a bit line precharge mechanism of the semiconductor memory device.

In a dynamic operation type semiconductor memory device, when reading data from each memory cell, the bit line is precharged and then discharged according to the memory cell data, and the state of the bit line corresponding to the memory cell to be read at that time is changed to that memory cell. It is read out as data. Therefore, a dynamic operation type semiconductor memory device is provided with a bit line brittleage mechanism for this purpose.

[Prior Art] Conventionally, in a semiconductor memory device of a dynamic operation type having a MOS transistor configuration, for example, a dynamic ROM circuit as shown in FIG. ) 1 has its respective source connected to the corresponding bit line 81, B2, 83.84,
A drain is connected to a precharge power supply CC. A precharge signal input line 2 is connected to the gate of each MO3Tr1 for precharging, and a precharge signal Φ1 shown in FIG. 4 is input to the input line 2. In addition, each bit line 81 to B4 has an enhancement WMO8Tr3 for discharge and five MO8Ts of a predetermined combination of enhancement type or depletion type.
Memory cells formed by connecting r4 in series are connected. And each M except for MO8Tr3 for discharge.
The gates of O3Tr4 are connected to word lines WO-W and 1 extending from the word line decoder, respectively. or,
The gate of each MO8Tr 3 for discharge is connected to a discharge signal input line 5, and the input line 5 is connected to the precharge signal input line 2 via an inverter circuit 6.

Each bit line 81 to B4 on the side opposite to the precharge MO8Tr1 has an enhancement type MO3 for selection.
Tr7 are connected to each other, and each MO3Tr7 is connected to one output line 8 shared by each bit line 81 to B4. The gates of each selection MO8Tr7 are connected to corresponding word lines W5 to W8, respectively.

The output line 8 is connected to a decoder 10 via an inverter circuit 9.
The decoder 10 is connected to the decoder 10 so that data from each block having the same circuit configuration consisting of a plurality of other memory cells is also input. This is an enhancement type P-channel M, 08Tr for compensating for high levels.

In the dynamic ROM circuit configured in this way, when reading data from each memory cell, H
When a level precharge signal of 1 is output, each MO3Tr1 for precharging becomes conductive, each MO3Tr3 for discharging becomes nonconductive, and all bit lines 81 to B
4 is precharged. Subsequently, when the precharge signal 1 is inverted to L level, each MO3 for precharging
Tr1 becomes non-conductive, and each MO3T for discharge
r3 is rendered conductive and discharged.

During this precharging and discharging, a bit line is selectively selected by the address signal input to each word line WO-W8, and the state of the bit line, that is, the data of a predetermined memory cell is transferred to the output line 8. is output to.

[Problems to be Solved by the Invention] However, in this dynamic ROM circuit, every time the precharge signal Φ1 goes to H level, all bit lines 81 to B/l, that is, unnecessary bit lines other than the selected one The precharge voltage is simultaneously applied to all the bit lines. That is, when the threshold voltage of MO3Tr1 for precharging is vth, and the logic value H level (plus potential) value of the precharge signal Φ1 inputted to G1~ is CC, the precharge voltage V prb is prb=VC
Take C-Vth.

Since this voltage Vprb is precharged with zero rigidity on each bit line 81 to B4, power consumption for precharging is large. Furthermore, each bit line that is unnecessarily precharged has the problem of generating unnecessary transient currents during precharging and discharging.

SUMMARY OF THE INVENTION An object of the present invention has been made to solve the above problems, and it is an object of the present invention to provide a semiconductor memory device that can reduce power consumption for precharging and reduce transient current during precharging and discharging. is.

[Means for Solving the Problems] In order to achieve the above object, the semiconductor memory device of the present invention has a precharge mechanism that applies a precharge voltage to each bit line all at once by reducing the amount of precharge. A reduction means is formed.

Each bit line is precharged to a small extent by the reduction means.

On the other hand, a precharge power supply is connected via a second precharge MOS transistor to an output line for data transfer shared by each bit line selectively selected by the selection MoS transistor. This second precharge MO
Only one selection MO3l selectively selected by the precharge power supply through the S transistor to the bit line selected through the transistor is precharged.

[Operation] A precharge power supply performs a precharge voltage on the bit line corresponding to one selectively selected MOS transistor through a precharge mechanism and a second precharge MOS transistor. Since the other unselected bit lines are precharged less from the precharge mechanism, the power consumption is reduced as a rest, and the transient current generated during precharging and discharging is reduced in unnecessary bit lines. can be made smaller.

[Embodiment 1] An embodiment in which the present invention is embodied in a dynamic ROM will be described below with reference to FIG.

Since this embodiment is characterized by the precharge mechanism of the dynamic ROM circuit, the precharge mechanism will be explained in detail and compared to the conventional dynamic ROM circuit shown in FIG.
Components that are the same as the M circuit are given the same symbols and detailed explanations are omitted for the sake of convenience.

In FIG. 1, MO3Tr1 for each precharging
The precharge signal input line 2 connected to the gate of is connected to the source of an enhancement type MO8Tr 21 serving as a reduction means. The precharge power supply Vcc is applied to the drain of this MO8Tr21, and the fourth
In the figure, a precharge signal of 1 is input. The H level of this bridle charge Φ1 is the precharge power supply Vcc.
is set to be at the same level. At this time,
If the threshold voltage of MO3Tr21 is vth, the same M
The source voltage of O8Tr21, that is, the gate voltage Vg applied to the data I- of MO3Tr1 for precharging.
H; tVc11=Vcc-Vth.

Therefore, the threshold of MO3Tr1 for precharging
! When the voltage is the same <Vth, the voltage at the source of MO3Tr1, that is, the voltage Vpra applied to each bit line B1 to B4 from this precharge mechanism is Vl)ra
=Va1-Vth=VCC-2Vth. Therefore,
Precharge voltage Vprb (=Vcc-Vt) applied to each bit line 81 to B4 from a conventional precharge mechanism
h).

Further, the drain of an enhancement type P-channel MO3Tr 22 as a second precharge MO3Tr is connected to one output line 9 shared by each bit line 81 to 3n, and the source of the MO8Tr 22 is connected to the precharge power supply. Vcc is connected. The second precharge MO3Tr 22 is connected to the second precharge signal input line 23
is connected to the input line 23, and a precharge signal Φ1 is inputted to the input line 23 via an inverter circuit 24.

Now, in the dynamic ROM configured as above,
When a predetermined address signal is output to W8 to each word line WO, MO3Tr7 for predetermined selection becomes conductive, a predetermined bit line (temporarily assumed to be bit line B1) is selected, and a predetermined memory cell is selected. is selected.

On the other hand, along with this, the H level precharge signal Φ1
is output, MO8Tr21 becomes conductive, each precharge MO3Tr1 becomes conductive, and each bit Il! B1 to B4 are precharged. At this time, M
The gate voltage Vg1 applied to the gate of MO3Tr1 for precharging via O3Tr21 is Vcll=V
cc -V th, and the precharge voltage Vl applied to each bit line 81 to B4 via the MO8Tr1)
ra (=VCC-2Vth), and a voltage lower than the conventional precharge voltage y prb (-Vcc-vth>) is applied to each bit line 81 to B4.

In addition, in response to the H level precharge signal Φ1, the second
The precharge MO3Tr 22 becomes conductive, and the precharge voltage vprC is applied from the precharge power supply ycc to only the selected bit line B1 via the output line 8 and the selection MO3Tr 7 which is in the conductive state, and is precharged.

Therefore, bit line B1 has both precharge voltages ypr
The sum of a and yprc is applied to provide sufficient precharging for data reading.

Then, when the precharge signal Φ1 changes from the H level to the L level, both MO8Tr1. MO3T
r22 becomes non-conductive, MO3Tr3 for discharge
conducts. At this time, select 1 is connected to bit line B1.
~ Depending on the state of the memory cell selected by the signal, the bit line B1 is discharged via the discharge MO3Tr3 and held at the L level, or is not discharged and held at the H level, and the level state is output as data to the output line. 8 is output.

As described above, in this embodiment, a lower precharge voltage vpra is applied to each bit line 81 to B4, so that the precharge amount is small and the selected bit line B1 is
Since precharging is performed separately via the selection MO3Tr 7 which is selectively selected from the output horn line 8 and is in a conductive state, the overall power consumption is small and the power consumption can be reduced. Also, other unselected bit lines 82
Since the transient current generated during precharging and discharging at ~B4 is small, it is possible to reduce the excessive S current as a whole.

Note that in this embodiment, there is no particular limitation on the size of the precharge voltages ypra and Vprc applied to the bit line, but the smaller the precharge voltage Vpra, the more the power consumption for precharging and the transient current are reduced. However, the precharge voltage V pr
It is necessary to increase c, and both values may be changed as appropriate within a range that does not interfere with data reading. In this case, one MO3Tr21 was used as a reducing means, but by connecting a plurality of MO3Tr21 in multiple stages, the precharge voltage ypr
The value of a may be changed as appropriate. Further, the reducing means is not limited to MO3Tr21, and the point is that it is sufficient to reduce unnecessary precharge m to the bit line, for example, by reducing the dimension of MO3Tr 1 for precharging, It may be implemented with appropriate changes such as connecting a resistor to the charging MO3Tr1.

Furthermore, 9. is a dynamic operation type semiconductor device having a memory cell structure other than the memory cell structure of the above embodiment. Of course, it is also possible to implement it in a device.

[Effects of the Invention] As described above (details) 21S, according to the present invention, each bit line is precharged to a small extent, and a selected bit line is additionally provided with an output line and a transistor from MO8l for selection. Since precharging is performed using a separate precharge power supply via the precharge power supply, it is possible to reduce power consumption for precharging and reduce transient current.

[Brief explanation of the drawing]

Fig. 1 is a dynamic ROM circuit diagram showing an embodiment embodying the present invention, Fig. 2 is a main part circuit diagram of a precharge mechanism, Fig. 3 is a conventional dynamic ROM circuit diagram, and Fig. 4 is a precharge circuit diagram. This is a signal waveform diagram. In the figure, 1 is a MOS transistor for precharging, 7 is a MOS l-ranshitor for selection, 8 is an output line, 21 is a MOS transistor as a reduction means, 22 is a second MOS transistor for precharging, B1 - B4 is a bit line, ycc is a precharge power supply, Fig. Conventional dynamic ROM circuit circuit diagram Waveform diagram of Britisage official name ■=

Claims (1)

[Claims] 1. Precharge each bit line (B1 to B4) by simultaneously turning on the precharging MOS transistors (1) connected to each bit line (B1 to B4). A precharge mechanism is provided, and the precharge MO
Each selection MOS transistor (7) connected to each bit line (B1 to B4) across the S transistor (1) and the bit line (B1 to B4) is selectively made conductive, and each bit line In the semiconductor memory device that selects one of the bit lines (B1 to B4) and outputs data to an output line (8) shared by each bit line (B1 to B4), the precharge mechanism includes the bit line (B1 to B4). ) is formed, and a precharge power supply (Vcc) is connected to the output line (8) via a second precharge MOS transistor (22). A semiconductor memory device characterized by: