JPH02127034U - - Google Patents
Info
- Publication number
- JPH02127034U JPH02127034U JP1989036807U JP3680789U JPH02127034U JP H02127034 U JPH02127034 U JP H02127034U JP 1989036807 U JP1989036807 U JP 1989036807U JP 3680789 U JP3680789 U JP 3680789U JP H02127034 U JPH02127034 U JP H02127034U
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- chip
- conductive
- plated
- conductive lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
Landscapes
- Wire Bonding (AREA)
Description
第１図〜第３図はこの考案をチツプオンボード
方式に適用した第１実施例を示し、第１図はメツ
キを施す際の絶縁基板の平面図、第２図は凹溝を
形成した絶縁基板の平面図、第３図はＩＣチツプ
を接合した状態の断面図、第４図および第５図は
この考案をＴＡＢ方式に適用した第２実施例を示
し、第４図はメツキを施す際のフイルム基板の平
面図、第５図はフイルム基板にＩＣユニツトを接
合した状態の断面図である。
１…絶縁基板、２…導電リード、３…接続パツ
ド、４，１１…凹溝、５，１５…ＩＣチツプ、１
０…フイルム基板。
Figures 1 to 3 show a first embodiment in which this idea is applied to a chip-on-board system. FIG. 3 is a plan view of the board, FIG. 3 is a cross-sectional view of the state where the IC chip is bonded, FIGS. 4 and 5 show a second embodiment in which this idea is applied to the TAB method, and FIG. FIG. 5 is a plan view of the film substrate, and FIG. 5 is a cross-sectional view of the IC unit bonded to the film substrate. DESCRIPTION OF SYMBOLS 1... Insulating substrate, 2... Conductive lead, 3... Connection pad, 4, 11... Concave groove, 5, 15... IC chip, 1
0...Film substrate.
Claims (1)
、この導電リードが四方より集中する箇所に前記
各導電リードが導通する接続パツドを形成し、こ
の接続パツドにより導通した前記各導電リードに
メツキを施し、このメツキが施された各導電リー
ドに前記基板上に載置されたＩＣチツプの各電極
をボンデイングするＩＣチツプの接合構造におい
て、 前記基板に前記接続パツドの外周を囲む凹溝を
形成して前記導電リードと前記接続パツドの接続
を切断したことを特徴とするＩＣチツプの接合構
造。[Claims for Utility Model Registration] A large number of conductive leads are formed on a substrate, and connection pads are formed where the conductive leads are concentrated from all sides, and the conductive leads are electrically connected to each other. In an IC chip bonding structure in which each conductive lead is plated and each electrode of an IC chip placed on the substrate is bonded to each plated conductive lead, the outer periphery of the connection pad is attached to the substrate. A bonding structure for an IC chip, characterized in that a surrounding groove is formed to disconnect the conductive lead and the connection pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989036807U JPH02127034U (en) | 1989-03-30 | 1989-03-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989036807U JPH02127034U (en) | 1989-03-30 | 1989-03-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02127034U true JPH02127034U (en) | 1990-10-19 |
Family
ID=31543364
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989036807U Pending JPH02127034U (en) | 1989-03-30 | 1989-03-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02127034U (en) |
-
1989
- 1989-03-30 JP JP1989036807U patent/JPH02127034U/ja active Pending
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