JPH021270B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a level detection circuit, and more particularly to a circuit configuration for enabling switching of a large number of detection levels according to the state of an input signal in a dynamic type level detection circuit. All of the following explanations will be made using an N-channel MOS field-effect transistor (hereinafter referred to as MOST), but this is for convenience of explanation; for example, a P-channel MOS field-effect transistor may be used, or any other type of isolated type field-effect transistor may be used. The same is true. A conventional dynamic type level detection circuit is shown in FIG. 1, and its operating waveforms are shown in FIG. The operation of the conventional level detection circuit shown in FIG. 1 will be described below using the operating waveforms shown in FIG. 2. However, the explanation will be made on the assumption that all the threshold voltages of the MOSTs used here are equal to V _T , but this is for convenience to make the explanation easier to understand. First, reset signal terminal P1 is set to high level (voltage
V _DD ), the nodes N1, N2, and N3 are at low level (ground voltage), and the output signal terminal OUT is at high level (from the power supply voltage V _DD to the MOST threshold voltage V _T
(voltage minus). Next, the reset signal terminal P1 is set to a low level to keep the nodes N1, N2, N3 and the output signal terminal OUT in a floating state, and the input signal v _a is applied to the input signal terminal IN. Then, MOST T ₁₁ becomes conductive from time t ₁ when the input signal v _a starts to become larger than the threshold voltage V _T of MOST T ₁₁ , and the potential at node N1 starts to rise. Furthermore, the potential of node N1 is
When it becomes larger than the threshold voltage V _T of MOST T ₂₁ ,
MOST T ₂₁ becomes conductive and the potential at node N2 begins to rise (time t ₂ ). At this time, the voltage level of the input signal v _a is as follows, since the potential of the node N1 is V _T .
It is now 2V _T , which is even higher by V _T than that. Similarly, when the potential of node N2 becomes V _T , MOST T ₃₁
becomes conductive, and the potential at node N3 begins to rise (time t ₃ ). The voltage level of the input signal v _a at this time is
It is 3V _T. Furthermore, when the potential of node N3 becomes higher than V _T (time t ₄ ), MOST BT ₁ becomes conductive and begins to discharge the charge stored between the drain of MOST BT ₁ and the source of MOST BT ₂ . The potential of the output signal terminal OUT decreases to a low level. The voltage level of the input signal v _a at this time is
It is set to 4V _T. Therefore, this circuit requires input signal
It can also be seen that the purpose is to detect the time (t ₄ ) when the input signal v _a becomes 4V _T when the final voltage level V _A of v _a becomes 4V _T or higher. Also, the potential of each node N1, N2, N3 is (V _A −V _T ),
(V _A −2V _T ), (V _A −3V _T ). As described above, in order to detect the time when the input signal v _a becomes 3V _T or 2V _T , it is necessary to remove MOST T ₁₁ and apply the input signal v _a directly to the node N1, or to
This was done by removing T ₂₁ and applying the input signal v _a directly to node N2. Also the input signal
If V _a is greater than 4V _T , MOST T ₁₁ ,
If we increase the number of T ₂₁ , T ₃₁ and T ₁₂ , T ₂₂ , T ₃₂ by connecting them in such a way that the operation described above is performed,
We were able to increase the detection level to 5V _T , 6V _T ,..., nV _T . The conventional level detection circuit illustrated in FIG. 1 has been described in detail above. However, these are all 1
One circuit can detect only one type of level, and in order to detect several types of levels according to the state of the input signal v _a , the same number of circuits as the number of the types are required. The present invention can be explained using the _symbols of the conventional example explained above.
By short-circuiting the gate of MOST T ₁₁ , node N1, node N2, and node N3 and controlling the voltage drop due to MOST T ₁₁ , T ₂₁ , and T ₃₁ , the above drawback can be removed and the state of input signal v _a Even when setting several types of detection levels depending on the number of levels, we have developed a level detection circuit that can detect many different levels with one circuit by adding a small amount of MOST depending on the number of levels. This is what we are trying to provide. According to the present invention, as shown in FIGS. 3 and 4, the first input terminal A _i , the second input terminal B _i , the third input terminal C _i , and the first output terminal D _i , a second output terminal E _i , a third output terminal F _i , and a connection terminal V _D to the first power supply n (i=1, 2, . . .
n-1, n, an integer of n≧1) signal generation circuits S _i
A level detection circuit consisting of n transfer gates GT _i , a first output transistor BT ₁ and a second output transistor BT ₂ , the first input terminal A of the i-th stage signal generation circuit S _{i i} is connected to the first output terminal D _{i-1 of the previous stage signal generation circuit S i- 1} and also connected to the drain of the i-th stage transfer gate _{GT i} , and The third input terminal C _i is connected to the third output terminal F _i-1 of the previous stage signal generation circuit S _i-1 , and the second output terminal E _i of the i-th stage signal generation circuit S _i is connected. A first output terminal is connected to the gate of the i-th transfer gate GT _i , and the sources of all n transfer gates GT _i are commonly connected to the first output terminal D _o of the final stage signal generation circuit S _o .
and the source of _{the first output transistor BT 1 is} grounded;
The drain of the first output transistor BT ₁ is connected to the source of the second output transistor BT ₂ and also to the output signal terminal OUT, and the gate of the second output transistor BT ₂ and all n signal generation circuits are connected. The second input terminal B _i of S _i is commonly connected to the reset signal terminal P1, and the drain of the second output transistor BT ₂ is connected to a second power supply application terminal that is equal to or different from the first power supply. V _E and the connection terminal V _D to the first power supply of all n signal generation circuits S _i are connected in common and connected to the first power supply application terminal V _DD , and the first stage signal generation circuit S Connect the first input terminal A ₁ of ₁ to the input signal terminal IN,
the third input terminal C ₁ of the first stage signal generation circuit S ₁
is connected to the detection level setting signal terminal P2, and all n signal generation circuits S _i connect the drain of the first transistor T _i1 to the connection terminal V _D to the first power supply, and The gate of one transistor T _i1 is connected to the first input terminal A _i , the source of the first transistor T _i1 is connected to the drain of the second transistor T _i2 , and the first output terminal D _i and said second transistor
connecting the gate of T _i2 to the second input terminal B _i ;
the source of the second transistor T _i2 is grounded;
The drain of the third transistor T _i3 is connected to the connection terminal V _D to the first power supply, the gate of the third transistor T _i3 is connected to the third input terminal C _i , and the third The source of the transistor T _i3 is connected to the drain of the fourth transistor T _i4 and also connected to the third output terminal F _i , and the gate of the fourth transistor T _i4 is connected to the second input terminal.
B _i , the source of the fourth transistor T _i4 is grounded, the drain of the fifth transistor T _i5 is connected to the connection terminal V _D to the first power supply, and the fifth transistor T _i5 The gate of the fifth transistor is connected to the second input terminal B _i , and the gate of the fifth transistor is connected to the second input terminal B i.
The source of T _i5 is connected to the drain of a sixth transistor T _i6 and also connected to the second output terminal E _i , and the gate of the sixth transistor T _i6 is connected to the third output terminal F _i . , a level detection circuit characterized in that the source of the sixth transistor T _i6 is grounded. The present invention will be explained in detail below using typical examples. FIG. 5 shows an example of a three-stage connection in which the present invention is implemented with n=3. Components equivalent to those in FIG. 1 are given the same reference numerals for convenience. FIG. 6 shows voltage waveforms of the main parts of FIG. 5. In FIG. 5, MOST T ₁₁ , T ₁₂ , T ₁₃ ,
T ₁₄ , T ₁₅ , and T ₁₆ are suffixed to mean the first, second, third, fourth, fifth, and sixth transistors constituting i=1st stage signal generation circuit S ₁ , respectively. It has been done. Similarly, T ₃₂ is the third stage signal generation circuit.
It means the second transistor of S ₃ and GT ₂
means the second stage transfer gate. Further, the nodes A ₁ , B ₁ , C ₁ , D ₁ , E ₁ , F ₁ are the first, second, third input terminals and the first, second, third input terminals of the first stage signal generation circuit S ₁ . The output terminal of is simply called a node. Similarly, the node _D3 is the first output terminal of the third stage signal generating circuit _S3 . Again, it is assumed that the threshold voltages of the MOSTs used are all equal to V _T , but this is the same as in the conventional example, and this assumption is for convenience of explanation and does not limit the present invention. Of course not. In this embodiment, in order to detect the time when the input signal v _a passes V _T , the transfer gate GT ₁
It is best to make it conductive. Then node A ₁ and
Since D ₃ is short-circuited, the input signal v _a is applied directly to the gate of the output transistor BT ₁ . Therefore, when the input signal v _a becomes larger than V _T , the output transistor BT ₁ becomes conductive, so the output signal terminal
The potential of OUT decreases. Similarly, in order to detect the time when the input signal v _a exceeds 2V _T , transfer gate GT ₁ should be made non-conductive and transfer gate GT ₂ should be made conductive, and at this time nodes A ₂ and D ₃ are Since it is short-circuited, the input signal v _a
An output signal is obtained at the output signal terminal OUT at a voltage level that makes MOST T ₁₁ and output transistor BT ₁ conductive at the same time, that is, at 2V _T.
Furthermore, if transfer gates GT ₁ and GT ₂ are made non-conductive and transfer gate GT ₃ is made conductive, the input signal _{v a} will be lower than the voltage level drop at MOST T ₁₁ and T ₂₁ and output transistor BT ₁ , that is, 3V _T. When it becomes large, an output signal is obtained. Also, MOST T ₁₃ , T ₁₄ , T ₁₅ , T ₁₆ , T ₂₃ ,
The signal generation circuit S ₁ , S ₂ , and S ₃ consisting of T ₂₄ , T ₂₅ , T ₂₆ , T ₃₃ , T ₃₄ , T ₃₅ , and T ₃₆ performs detection according to the voltage level applied to the detection level setting signal terminal P2. Generate level switching signal and transfer gate GT ₁ ,
This is to be added to GT ₂ and GT ₃ . The operation of the circuit shown in FIG. 5 will now be explained using the operating waveforms shown in FIG. 6. When the reset signal terminal P1 is at high level, the nodes A ₂ , A ₃ , D ₃ , C ₂ , C ₃ and F ₃ are at low level, so MOST T ₂₁ , T ₃₁ , T ₁₆ , T ₂₆ , T ₃₆ ,
T ₂₃ , T ₃₃ and the output transistor BT ₁ become non-conductive, and the nodes E ₁ , E ₂ , E ₃ and the output signal terminal OUT become high level. Therefore, when the reset signal terminal P1 is set to a low level, all nodes become floating. However, at this time, it is assumed that the detection level setting signal terminal P2 is at a low level. Here, the detection level setting signal terminal P2 is set to a constant level V _P2 . Then, as explained earlier, the potentials of nodes C ₂ , C ₃ , and F ₃ are (V _P2 −V _T ), respectively.
(V _P2 −2V _T ) and (V _P2 −3V _T ), but these are never negative. In other words, when V _P2 is 2.5V _T , the potentials of nodes C ₂ , C ₃ , and F ₃ are respectively
1.5V _T , 0.5V _T , 0. Also, the nodes E ₁ , E ₂ ,
To bring E ₃ to a low level, i.e. MOST T ₁₆ ,
In order to make T ₂₆ and T ₃₆ conductive, nodes C ₂ and
It is sufficient if the potentials of C ₃ and F ₃ are each equal to or higher than V _T .
Therefore, the node E ₁ becomes low level when the condition (V _P2 −V _T )>V _T ∴V _P2 >2V _T is satisfied. Similarly, nodes E ₂ and E ₃
becomes a low level when V _P2 satisfies the following conditions. (V _P2 −2V _T )＞V _T ∴V _P2 ＞3V _T (V _P2 −3V _T )＞V _T ∴V _P2 ＞4V _TIn this way, the detection level is set after the reset signal terminal P1 becomes low level. When the voltage level of the signal terminal P2 is fixed at a constant level V _P2 , the levels of the nodes E ₁ , E ₂ , and E ₃ are determined according to the magnitude of the level V _P2 . This relationship is summarized in the table below, with high levels indicated by H and low levels indicated by L.

[Table] Therefore, when the voltage level V _P2 of the detection level setting signal terminal P2 is lower than 2V _T , the node E ₁ becomes high level and the transfer gate GT ₁ becomes conductive, so as mentioned above, the nodes A ₁ and D ₃ is short-circuited and the voltage level of the input signal v _a is greater than V _{T 1}
The potential of the output signal terminal OUT decreases. Also V _P2
When is more than 2V _T and lower than 3V _T , node E ₁ becomes low level and therefore transfer gate GT ₁ becomes non-conductive, but node E ₂ becomes high level and transfer gate GT ₂ becomes conductive. Nodes A ₂ and D ₃ are shorted, resulting in an output signal at time t ₂ when the voltage level of input signal v _a becomes greater than 2V _T. Similarly, when V _P2 is higher than 3V _T and lower than 4V _T , transfer gates GT ₁ and GT ₂ are non-conductive and transfer gate GT ₃ is conductive, so the time when the voltage level of input signal v _a reaches 3V _T is determined. An output signal is obtained at t ₃ . When V _P2 is 4V _T or higher, nodes E ₁ , E ₂ , and E ₃ become low level, so transfer gates GT ₁ , GT ₂ , and GT ₃ become non-conductive, and the voltage level of input signal v _a becomes 4V _T. An output signal is obtained from the output signal terminal OUT at time _t4 . According to the above-mentioned idea, in this embodiment, there are four types of detection levels, but by adding some MOST, it is possible to set a detection level that is an integral multiple of the threshold voltage V _T of the MOST. Also, the maximum voltage level V _A of the input signal v _a and the detection level setting signal terminal P2
When the voltage level of V _P2 is taken to be equal to the voltage level of V _P2 , the detection level is approximately nV _T <
The voltage level nV _T satisfies V _A. However, n is the largest integer excluding zero. By doing this, an output signal is always obtained whenever V _A has a voltage level higher than V _T . As described in detail above, the present invention provides a dynamic level detection circuit with the addition of a few MOSTs and a detection level switching signal generation circuit.
It has the advantage that several types of levels can be detected with one circuit, and that an output signal can always be obtained by detecting a level corresponding to the maximum voltage level of the input signal, regardless of whether the input signal is high or low.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing a conventional level detection circuit.
Figure 2 is an operating waveform diagram of the circuit in Figure 1, Figure 3 is a block diagram showing the configuration of the present invention, Figure 4 is a circuit diagram showing the internal configuration of the blocks used in Figure 3, and Figure 5. 6 is a circuit diagram showing an embodiment of the present invention, and FIG. 6 is an operation waveform diagram of each part of the circuit of FIG. 5. In the figure, IN is an input terminal; OUT is an output signal terminal; P1 is a reset signal terminal; P2 is a detection level setting signal terminal; V _DD and _VE are power supply terminals; BT ₁ and BT ₂
is an output transistor; GT _i is a transfer gate; S _i is an i-th stage signal generation circuit; A _i , B _i , C _i , D _i ,
E _i and F _i are terminals of the i-th stage signal generation circuit S _i ; T _i1 ,
T _i2 , T _i3 , T _i4 , T _i5 , _and T _i6 are the first, second, third, fourth, and
The fifth and sixth transistors are shown.

Claims (1)

[Claims] 1 first input terminal A _i , second input terminal B _i , third input terminal
_{n ( i = 1} ,2,...,n
-1, n, an integer of n≧1) signal generating circuits S _i , n transfer gates GT _i , a first output transistor BT ₁ , and a second output transistor BT ₂ . Then, the first input terminal A _i of the i-th stage signal generation circuit S _i is connected to the first output terminal D _i-1 of the previous stage signal generation circuit S i _- 1, and
The third input terminal C i of the i-th stage signal generation circuit S _i is connected to the drain of the transfer gate GT _i of the ith stage, and the third output terminal of the previous stage signal generation circuit S _{i -1} is connected to the drain of the transfer gate GT i of the ith stage.
F _i-1 , the second output terminal E _i of the i-th stage signal generation circuit S _i is connected to the gate of the i-th stage transfer gate GT _i , and all n transfer gates GT _i source and final stage signal generation circuit
The first output terminal D _o of S _o is commonly connected to the gate of the first output transistor _{BT 1, the source of the first output transistor BT 1 is} grounded, and the first output transistor BT ₁ drain to 2nd
is connected to the source of the output transistor BT ₂ and to the output signal terminal OUT, and the gate of the second output transistor BT ₂ and the second input terminal B _i of all n signal generation circuits S _i are connected in common. The drain of the second output transistor _BT2 is connected to a second power supply application terminal _VE that is equal to or different from the first power supply, and all n signal generation circuits are connected to the reset signal terminal P1. The connection terminal V _D to the first power supply of S _i is commonly connected to the first power supply application terminal V _DD , and the first input terminal A ₁ of the first stage signal generation circuit S ₁ is connected to the input signal terminal. IN, and the third input terminal C ₁ of the first stage signal generation circuit S ₁ is connected to the detection level setting signal terminal P 2 , and all n signal generation circuits S _i are connected to the first transistor The drain of T _i1 is connected to a connection terminal V _D to a first power supply, the gate of the first transistor T _i1 is connected to the first input terminal A _i , and the first
The source of the transistor T _i1 is connected to the drain of the second transistor T _i2 and also connected to the first output terminal D _i , and the second transistor T _i2
The gate of the second transistor T i2 is connected to the second input terminal B _i , the source of the second transistor T _i2 is grounded, and the third
The drain of the transistor T _i3 is connected to the connection terminal V _D to the first power supply, the gate of the third transistor T _i3 is connected to the third input terminal C _i , and the third transistor T _i3 source 4th
The gate of the fourth transistor T _i4 is connected to the drain of the transistor T i4 and the third output terminal F _i , the gate of the fourth transistor T _i4 is connected to the second input terminal B _i , and the fourth transistor T The source of the _fifth transistor T i5 is grounded, the drain of the fifth transistor T _i5 is connected to the connection terminal V _D to the first power supply, and the gate of the fifth transistor T _i5 is connected to the second input terminal B _i . The source of the fifth transistor T _i5 is connected to the drain of the sixth transistor T _i6 and also connected to the second output terminal E _i , and the gate of the sixth transistor T _i6 is connected to the third connected to the output terminal F _i of the sixth transistor
A level detection circuit characterized in that it is constructed by grounding the source of a T _i6 .