JPH02127739A - Cpu monitor circuit - Google Patents

Abstract

PURPOSE:To attain the accurate output of the desired pulse width by counting the clocks as the digital value in the number equal to the number of counter stages and monitoring a CPU based on the clock counting result. CONSTITUTION:A counter 1 connects the monitor pulse input received from a CPU to a load input terminal L and at the same time fixes the highest rank terminal 1(n) of the N-notation parallel load input at logic 'H'. A flip-flop 2 connects the reset signal of the CPU to a set terminal S and at the same time connects the output of the CPU to a clear input terminal CRL of the counter 1. Therefore, the CPU monitor pulse input width necessary for detection of the cut of the CPU monitor pulse output of the counter 1 undergone the N notation which is received from an output terminal 6 can be decided from the count value (N - n) obtained by setting externally and optionally the parallel load input (n) to the N-notation parallel load 1 (1) - 1(n) and the clock interval impressed to a clock input terminal CLK. As a result, the desired output pulse width is accurately obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to the field of application of digital logic circuits.
This paper relates to CPU monitoring of digital equipment using C#1 logic circuits.

(Prior Art) Generally, a CPU monitoring circuit uses a monostaple multivibrator, which is designed to apply an input pulse and then obtain an arbitrary predetermined output pulse width. Conventional monostaple multivibrators accomplish this goal by setting a time constant based on the integral action of the pulses. That is, one resistor and IW
This objective is achieved by an integrating circuit with capacitor A. In other words, it is designed to connect a predetermined voltage source 1, for example, a power supply, with the input pulse application time as the start time, start the integral action, find out the time when the integrated voltage reaches a predetermined value, and obtain the output pulse width during this time. has been done. In general, a mono-staple multivibrator integrated as individual parts is developed and commercially available, and an example is shown in the wXa diagram.

@8 In the diagram, 7 is a monostable multivibrator, 8 is a resistor, and 9 is a capacitor.

In the example shown in FIG. 8 as well, the external resistor 8 and capacitor 9 are selected to have appropriate values, and the output pulse width is obtained in relation to the time constant obtained by the integration.

(Problems to be Solved by the Invention) In the above-described conventional monostaple multivibrator used in a general KCPU monitoring circuit, the output pulse width depends on the above-mentioned time constant and the value of the power supply voltage.

Generally, when a multivibrator is integrated, this voltage source becomes the power supply voltage of the integrated circuit, so the output pulse width cannot be changed by the voltage source. Also, since the six values of resistors and capacitors are generally fixed, the output pulse width corresponding to these values is also fixed. Therefore, in applications where a desired pulse width is to be obtained by external control, there is a drawback of a lack of flexibility. Also, since there is only one pulse output for one input, if only a small number of charges are connected to the multivibrator, it will not be possible to generate 7 pulses. Furthermore, although the above-mentioned time constant is determined by six values of the resistor 4 and the capacitor, there is a drawback that the desired output pulse width cannot be obtained accurately due to the paramutation of these values.

An object of the present invention is to eliminate the above-mentioned drawbacks by counting the number of clocks as a digital value by the number of counter stages and using this to monitor the CPU. There is a circuit for visual circuits.

(Means for Solving the Problems) A circuit for CPU t viewing circuit according to the present invention is constructed by comprising a counter with a parallel load means and a flip-flop.

The input terminal with parallel load means connects the monitoring pulse input from the CPU to the load input terminal, connects the clock to the clock input terminal, and connects the highest terminal of the N-ary parallel load input to the logic %H#. It is fixed at .

The flip-flop has a CPU reset signal connected to a set terminal, the highest output of the input terminal connected to a reset terminal, and an output connected to a clear input terminal of an N-adjusted counter.

In the above configuration, the present invention provides the CP of the N-adjusted counter.
The CPU monitoring pulse input width for detecting disconnection of the U monitoring pulse output is input from the outside to the N-ary parallel CI -h' terminal 1.
/C can be determined by the count value (N-11)% arbitrarily set by the parallel load input n and the interval of the clock applied to the clock input terminal.

(Example) Next, one embodiment of the present invention will be explained with reference to the drawings.

Figure ta1 is a diagram showing an embodiment of the CPU monitoring circuit according to the present invention. In Fig. 1, 1 is an increment counter with parallel roto function, 1(1) to 1(n-1
) is a parallel data input terminal with a total value of n.%1(n) is the highest parallel data input terminal. 2 is a set-reset flip-flop; %3 is a CPU monitoring pulse input terminal;
4 is a clock signal input terminal, 5 is a CPU reset signal input terminal, and 8 is a CPU demand monitoring pulse output terminal (the highest output terminal of the counter).

FIG. 2 is a time chart showing the operation of the embodiment shown in FIG.

When resetting the CPU, the CPU reset signal input terminal s
Since the CPU reset pulse from is input to the set signal terminal S of the set reset flip 0 block 2,
The output of the flip-flop outputs a logic %H#. Theory f
The output of I1%H# is the clear terminal CLH of N-ary counter 1.
Since the counter 1 is connected to the counter 1, the counter 1 becomes deaf in the countable state.

The counter 1 starts counting from the next pulse that arrives at the clock signal input terminal 4. Immediately upon being reset, the CPU begins to output a self-monitoring pulse, and its output is input from the CPU monitoring pulse input terminal 3 to the load 7 of the counter 1.

It is connected to the highest terminal 1 of the parallel load input of the counter 1 (l is logical!! 1% Hl), so when a signal is input to the pulse input terminal 3 (at the same time as the pulse that arrives, the highest terminal of the counter The CPU monitoring pulse output terminal 6, which is the upper output terminal, outputs the logic %l(jF.When the CPU is operating normally, the CPU monitoring pulse is output from the CPU until the N-ary counter reaches (N-n) 9 nodes. Since the monitoring pulse is input to the pulse input terminal 3, the pulse output terminal 6 of the monitoring circuit continues to output the logical %H#.

On the other hand, the CPU becomes abnormal and the value of input 9 is (N-n).
If the pulse input from the CPU monitoring pulse input terminal 3 is cut off within the time limit, when (N-n+1) clock pulses are input from the clock signal input terminal 4, the pulse input from the CPU monitoring pulse output terminal 6 is interrupted. 1LI is output. Since the output of the CPU monitoring pulse output terminal 6 is input to the reset terminal of the set/reset clip-flop 2, the flip-flop 2 outputs #71@%Lβ.

Since the output of flip-flop 2 is connected to the clear terminal of counter 1, counter 1 stops the output.

Therefore, the pulse output terminal 6 maintains its state unless the CPU is reset.

In the above-described operation, the CPU monitoring pulse output is particularly obtained by providing a clock frequency and the number of counter stages arbitrarily from the outside instead of the time constant in the prior art.

(Effects of the Invention) As explained above, the present invention uses a logic circuit as one circuit configuration, increases the digital value, counts the number of clocks by the number of counter stages, and uses this to monitor the CPU. Not only can an arbitrary time constant be given more precisely depending on the accuracy of the clock frequency, etc., but also the time constant can be changed flexibly simply by converting the clock frequency. This has the effect that outputs can be obtained from a plurality of output terminals without increasing the number of circuits.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing an embodiment of a CPU monitoring circuit according to the present invention. FIG. 2 is a time chart of signals showing the operation of the circuit shown in FIG. Figure 8 shows a multivibrator 2〇PU according to the conventional technology.
FIG. 2 is a circuit configuration diagram showing an example of a monitoring circuit. 1... Counter 1 (1) to 1 rn) *... Parallel data input terminal 2... Set/reset flip 20 knob 3... CP
U monitoring pulse input terminal 4... Clock signal input terminal S, life, CPU reset input terminal 6... CPU monitoring monitoring pulse output terminal - Mono staple multivibrator 8... Resistor 9... Capacitor

Claims (1)

[Claims] The monitoring pulse input from the CPU is connected to the load input terminal, the clock is connected to the clock input terminal, and the highest terminal of the N-ary parallel load input is set to logic "H".
a counter with parallel loading means fixed to the C;
a flip-flop that connects a reset signal of the PU to a set terminal, connects the highest output of the counter to a reset terminal, and connects an output to a clear input terminal of the N-ary counter; A count value (N-n) is obtained by arbitrarily setting the CPU monitoring pulse input width for detecting disconnection of the CPU monitoring pulse output of the counter from the outside using the parallel load input n to the N-ary parallel load terminal. and a CPU monitoring circuit configured such that the determination can be made based on the interval of the clock applied to the clock input terminal.