JPH02128438A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPH02128438A
JPH02128438A JP63283021A JP28302188A JPH02128438A JP H02128438 A JPH02128438 A JP H02128438A JP 63283021 A JP63283021 A JP 63283021A JP 28302188 A JP28302188 A JP 28302188A JP H02128438 A JPH02128438 A JP H02128438A
Authority
JP
Japan
Prior art keywords
vss
vcc
wiring
integrated circuit
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63283021A
Other languages
Japanese (ja)
Inventor
Shinji Kawai
河井　伸治
Tomio Suzuki
富夫 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP63283021A priority Critical patent/JPH02128438A/en
Publication of JPH02128438A publication Critical patent/JPH02128438A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view

Landscapes

  • Read Only Memory (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 ［産業上の利用分野］ 本発明は一半導体集積回路のＶｃｃ−Ｖｓｓの供給方法
に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for supplying Vcc-Vss to a semiconductor integrated circuit.

〔従来の技術〕[Conventional technology]

＠２図に示しであるように一従来の半導体集積回路は−
Ｖｃｃ、　Ｖｓｓ端子から半導体基盤へは１箇所しかワ
イヤーボンドされていなかった。このためＶｃｃ　、　
Ｖｓｓ端子と反対側の半導体基盤上では−Ｖｃｃ−Ｖｓ
ｓ端子から離れているので、どうしてもＶｃｃ、Ｖｓｓ
配線につく寄生抵抗が大きくなり、Ｖｃｃ、　Ｖｓｓ配
線が高インピーダンスになっていた。したがって反対側
では、電圧降下が起きる。@2 As shown in Figure 2, a conventional semiconductor integrated circuit is -
There was only one wire bond from the Vcc and Vss terminals to the semiconductor substrate. For this reason, Vcc,
-Vcc-Vs on the semiconductor substrate opposite the Vss terminal
Since it is far from the s terminal, Vcc and Vss cannot be connected.
The parasitic resistance attached to the wiring had increased, and the Vcc and Vss wiring had become high impedance. A voltage drop therefore occurs on the opposite side.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来ノｖＣＣ，ｖＳＳノ供給方法テハ、Ｖｃｃ−Ｖｓｓ
配線につく寄生抵抗により配線が高インピーダンスにな
り、電圧降下が起きる。Conventional vCC, vSS supply method, Vcc-Vss
Parasitic resistance attached to the wiring makes the wiring high impedance, causing a voltage drop.

この発明は、上記のような問題点を解決するためになさ
れたもので、半導体基盤全体に低インピーダンスでＶｃ
ｃ、　Ｖｓｓを供給できる。This invention was made to solve the above-mentioned problems.
c, Vss can be supplied.

〔課題を解決するための手段］ この発明に係る、Ｖｃｃ、　Ｖｓｓの供給方法は、ダイ
パッド上の配線を通じて半導体基盤上の任意の部分ニ、
ｖＣＣ，ｖＳＳ端子カラＶＣＣ−ｖＳＳヲ供給供給スル
コマきる。[Means for Solving the Problems] A method for supplying Vcc and Vss according to the present invention provides a method for supplying Vcc and Vss to any part on a semiconductor substrate through wiring on a die pad.
When the vCC and vSS terminals are empty, the supply voltage between VCC and vSS is closed.

〔作用〕[Effect]

この発明におけるＶｃｃ−Ｖｓｓの供給方法は、ダイパ
ッド上の配線によって行なわれるので一低インピーダン
スでＶｃｃ−Ｖｓｓを供給することができる。The method of supplying Vcc-Vss in the present invention is performed by wiring on the die pad, so that Vcc-Vss can be supplied with a low impedance.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。第１
図は、その実施例を示す。まず、３のＶｃｃ配線−４の
ｖＳＳ配線を５のダイパッド上に一図のようｌこ配線す
る。ここでＶｃ＋、　Ｖｓｓ配線とダイパッド間は絶縁
しておく。そして−１−３間−３−７間、２−４間、４
−７間をワイヤーボンドしてやる。そうすれば、Ｖｃｃ
、　Ｖｓｓ端子の反対側にもＶｃｃ、Ｖｓｓ端子から直
接Ｖｃｃ−Ｖｓｓが供給できるので一半導体基盤全体に
低インピーダンスでＶｃｃ−Ｖｓｓの供給が可能になる
。An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows an example thereof. First, the Vcc wiring No. 3 and the VSS wiring No. 4 are wired on the die pad No. 5 as shown in the diagram. Here, the Vc+, Vss wiring and the die pad are insulated. And between -1-3 -3-7, between 2-4, and 4
I'll do a wire bond between -7. Then, Vcc
Since Vcc-Vss can be directly supplied from the Vcc and Vss terminals to the opposite side of the Vss terminal, Vcc-Vss can be supplied to the entire semiconductor substrate with low impedance.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば−ダイパッド上にＶｃ
ｃ、　Ｖｓｓ配線を作り、この配線を通してＶｃｃ、Ｖ
ｓｓを供給しているので、たとえ基盤の大きさが大きく
なっても半導体基盤のどこにでも低インピーダンスでＶ
ｃｃ、Ｖｓｓを供給できる。As described above, according to the present invention - Vc on the die pad
c, Vss wiring is made, and Vcc, V
SS is supplied, so even if the size of the board becomes large, V can be supplied anywhere on the semiconductor board with low impedance.
Can supply cc and Vss.

【図面の簡単な説明】[Brief explanation of the drawing]

＠１図は、この発明の一実施例を示す関−第２図は一従
来のＶｃｃ、Ｖｓｓの供給方法を示す図である。 第１　図ノ１　ハＶｃｃ端子−２１；！Ｖｓｓ端子−３
１ｔＶｃｃ配線−４はＶｓｓ配線−５はダイパッド、６
は半導体基盤、７はコンタクトホール、第２図において
、１はＶｃｃ端子、２はＶｓｓ端子、３はダイパッド、
４は半導体基盤である。 なお− 各図中同一符号は− 同一または相当部分 を示す。Figure 1 shows an embodiment of the present invention, and Figure 2 shows a conventional method of supplying Vcc and Vss. Fig. 1 No. 1 C Vcc terminal -21;! Vss terminal-3
1tVcc wiring-4 is Vss wiring-5 is die pad, 6
2 is a semiconductor substrate, 7 is a contact hole, 1 is a Vcc terminal, 2 is a Vss terminal, 3 is a die pad,
4 is a semiconductor substrate. Note that the same reference numerals in each figure indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] 半導体基盤全体に低インピーダンスでＶ＿ｃ＿ｃ、Ｖ＿
ｓ＿ｓを供給可能にするため、ダイパッド上に配線をほ
どこしたことを特徴とする半導体集積回路。V_c_c, V_ with low impedance across the entire semiconductor substrate
A semiconductor integrated circuit characterized in that wiring is provided on a die pad to enable supply of s_s.
JP63283021A 1988-11-08 1988-11-08 Semiconductor integrated circuit Pending JPH02128438A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63283021A JPH02128438A (en) 1988-11-08 1988-11-08 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63283021A JPH02128438A (en) 1988-11-08 1988-11-08 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH02128438A true JPH02128438A (en) 1990-05-16

Family

ID=17660198

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63283021A Pending JPH02128438A (en) 1988-11-08 1988-11-08 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH02128438A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62216240A (en) * 1986-03-17 1987-09-22 Nec Ic Microcomput Syst Ltd Package for integrated circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62216240A (en) * 1986-03-17 1987-09-22 Nec Ic Microcomput Syst Ltd Package for integrated circuit

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