JPH02128535A - Frame converting circuit - Google Patents

Abstract

PURPOSE:To surely convert the frame constitution and absorb the variance in input/output phase with a simple circuit constitution by using a high-speed and large-capacity dual port RAM having an input port and an output port individually. CONSTITUTION:A large-capacity dual port RAM 101 provided with the input port and the output port individually is used, and phases of a reference timing pulse and an input timing pulse 5 are compared with each other to select one of them. Consequently, the phase variance in bits and that with a bit as the unit of an input signal string, the input timing pulse 5, and an input clock 6 are controlled to absorb the phase of the digital signal string, and the write control and the read control are simultaneously performed for the same memory element. Thus, only one memory element is required, and frame conversion including frame phase absorption is performed in the small scale-circuit constitution.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a frame conversion circuit that performs phase absorption and frame conversion of a data signal sequence, and in particular, a frame conversion circuit that has separate input ports and output ports, and that performs write control. The present invention relates to a frame conversion circuit that has a simplified circuit configuration using a dual port RAM that can simultaneously perform read control and read control.

[Prior Art] FIG. 3 is a block diagram of a conventional frame conversion circuit.

In the figure, 201 is a phase absorption memory such as a FIFO memory, which absorbs phase fluctuations in an input signal sequence. Note that this writing and reading control is performed by the phase absorption memory control circuit 202. On the other hand, the signal sequence tuned to the output side phase is written to the first RAM 204 via the first buffer 203. This first RAM2
Writing to 04 is performed according to a write pulse from the control circuit 205 and a write address output from the write address generation circuit 206 and selected by the switching circuit 207.

Here, the write operation to the first RAM 204 is performed for one frame, and during that time the second RAM 208 receives the output from the read address generation circuit 209 and the switching circuit 2.
A read operation is performed according to the read address selected in step 09 and a control signal from the control circuit 205. The output read from this RAM 208 is sent to the selection circuit 210.
is input. Then, a signal line is selected by this selection circuit 210 and becomes an output signal string.

In the next frame, the operations of RAM 204 and RAM 208 are swapped. That is, the selection circuit 210 selects the RAM 20
Select the output line from 4 and switch circuits 207 and 209.
In this case, the write and read addresses are switched.

Therefore, data of a new input signal string is written to the RAM 208, and the contents written in the previous frame are read from the RAM 204.

The frame configuration conversion is performed by the address generation circuit 20 at this time.
6 and 208, and frame conversion is performed by performing these operations alternately for each frame.

Conventional frame conversion circuits perform frame conversion as described above.

[Problems to be Solved] The conventional frame conversion circuit described above had to alternately perform write control and read control for one RAM every cycle, and as a result, two RAMs were required. In addition to requiring control to switch input/output and addresses in two RAMs, there were also problems in that the circuit configuration was large and complex.

The present invention has been made in view of the above-mentioned problems, and uses a high-speed, large-capacity, dual-port RAM having separate input ports and output ports to configure a single RAM, and a frame including frame phase absorption. An object of the present invention is to provide a frame conversion circuit that can perform conversion with a small-scale circuit configuration.

[Means for Solving the Problems] In order to achieve the above object, the frame conversion circuit of the present invention has separate input ports and output ports, and is a dual port that simultaneously writes an input digital signal string and reads an output digital signal string. It performs read control of the RAM and this dual port RAM, and outputs and inputs a first control pulse of N frame period, a second control pulse delayed by M bits with respect to this first control pulse, and a judgment pulse. A digital signal train, an input timing pulse, a readout control circuit that controls phase fluctuations within a bit and in units of bits in an input clock, and the above-mentioned first control pulse and second control pulse are input, and one of them is selected. A selection circuit that outputs a control pulse, inputs the input timing pulse, the high-power clock, and the control pulse from the selection circuit, and inputs the N to the dual port RAM.
A write control circuit that performs write control by outputting a write address and a write control signal in units of frames, and also outputs phase information of an input timing pulse with respect to the control pulse, and a read control circuit that outputs phase information from the write control circuit and the read control circuit. and a determination circuit that inputs a determination pulse from the input timing pulse, determines the phase of the input timing pulse with respect to the control pulse, and controls the selection circuit.

[Example] Hereinafter, the present invention will be explained in detail based on the drawings.

FIG. 1 is a block diagram of a frame conversion circuit according to an embodiment of the present invention, and FIG. 2 is a timing chart of the frame conversion circuit shown in FIG.

In the figure, 101 is a dual port RAM;
It has separate input ports and output ports, and controls writing the input digital signal string 4 according to the write address 13 and the write control signal 14, and reading out the frame-converted output signal string 3 according to the read address 7 and the read control signal 8. can be done at the same time.

Next, 102 is a read control circuit, which inputs a reference timing pulse and a reference clock and outputs a read address 7 and a read control signal 8 with a frame period of N (N: a natural number of 2 or more), and reads the dual port RAM 10I. control. In addition, in order to control the phase fluctuations within and in bit units of the input digital signal train 4, the input timing pulse 5, and the input clock 6,
A first control pulse 9 with a period of N frames, and a second control pulse delayed by M (M: natural number) bits with respect to the first control pulse 9.
A control pulse 10 and a determination pulse 11 are output.

Further, 103 is a selection circuit which inputs the first control pulse 9 and the second control pulse 10, selects it according to the determination result 15, and outputs the control pulse 12.

On the other hand, 104 is a write control circuit which inputs an input timing pulse 5, an input clock 6, and a control pulse 12 with an N frame period, outputs a write address 13 with an N frame period and a write control signal 14, and outputs a write address 13 with an N frame period and a write control signal 14. Write control is performed. At the same time, the input timing pulse 50 phase information 16 for the control pulse 12 is output. A determination circuit 105 inputs the determination pulse 11 and phase information 16, determines the phase of the input timing pulse 5 with respect to the control pulse 12, and outputs the determination result 5 in order to control the selection circuit 103.

The operation of the frame conversion circuit having the above configuration will now be described assuming that the pulse width is one frame and the frame period is N=3.

First, on the input side of the dual port RAMIOI,
Based on the input timing pulse 5 and input clock 6 signals, the input digital signal string 4 is generated according to the write address 13 created by the write control circuit 104 and the control signals (enable signal, write clock, etc.) necessary for writing.
is written to the RAM 101. On the other hand, on the read side, the output signal string 3 is output from the RAM 101 by the read address 7 and read control signal 8 generated by the read control circuit 102 based on the read side reference frame pulse serving as a reference timing pulse and the read side clock 2. Read out. Depending on how the write address 13 and read address 7 are set at this time, the frame configuration can be swapped, and desired frame conversion can be achieved.

Next, the phase control operation will be explained using the timing chart of FIG.

In the figure, a is a reference timing pulse, b,
c is a first control pulse and a second control pulse created based on this. By the way, the selection circuit 10
3, the first control pulse a and the second control pulse C
One of them is selected according to the determination result 15 and output as the control pulse 12. Then, the write control circuit 10
4, this control pulse 12 and input timing pulse 5
The phase information 16 is created by comparing the two. For example, if the first control pulse b is selected and output as the control pulse 12, phase information g is output in response to the input timing pulse d.

In other words, both bipulse portions are output. However, if a pulse is output twice within three frames (N23) that are the write and read cycles as shown in g as phase information, the determination circuit 105 switches to the other second control pulse C. Then, the determination result 15 is outputted to the selection circuit 103. Then, in the selection circuit 103,
Based on this determination result 15, a second control pulse C is output.

Now, in the write control circuit 104, the second control pulse C and the input timing pulse d are compared, and a pulse of phase information J is output. Then, the write address 13 and the write control signal 14 are generated according to this phase information J. Therefore, as shown by the input timing pulse L, frames #1, #2, and #3 of the three frames in the write cycle are read out at positions #1, #2, and #3 of the reference timing pulse a or the read position, respectively. .

Furthermore, when the second control pulse C is selected as the control pulse, phase information I is output with respect to the input timing pulse f. However, in this phase state I, since a pulse is output twice within three frames, the determination circuit 105 outputs a determination result 15 to the selection circuit 103 so as to switch to the first control pulse b. In this way, the phase information J, that is, the writing period is controlled to be a three-frame period, and is always written one frame or more ahead of the read frame position. Therefore, absorption of phase fluctuations and frame conversion are possible.

In this way, in this embodiment, a large capacity dual port RA
By using M and selecting one of two types of control pulses based on the result of phase comparison between the reference timing pulse and the input timing pulse, the bit internal and It is possible to absorb the phase of a digital signal string by controlling phase fluctuations in units of bits, and write control and read control can be performed simultaneously on the same memory element, so only one memory element is required. Furthermore, control such as switching between write control and read control and switching between write address and read address is not required.

[Effects of the Invention] As explained above, the present invention uses a large-capacity dual-port RAM to easily and reliably convert frame configurations and absorb input/output phase fluctuations with a simple circuit configuration. This has the effect of providing a frame conversion circuit.

[Brief explanation of drawings]

FIG. 1 shows frame conversion O1 according to an embodiment of the present invention: 02= 03 = 042 05: dual port ram Read control circuit selection circuit Write control circuit Judgment circuit

Claims (1)

[Claims] A dual port RAM has separate input ports and output ports, and simultaneously writes an input digital signal string and reads an output digital signal string. A control pulse, a second control pulse delayed by M bits with respect to the first control pulse, and a judgment pulse are output to detect phase fluctuations within bits and in bit units in the input digital signal string, input timing pulse, and input clock. a readout control circuit for controlling; a selection circuit for inputting the first control pulse and the second control pulse, selecting one of them and outputting the control pulse; the input timing pulse and the input clock; and the selection circuit. a write control circuit that inputs a control pulse from the dual port RAM and outputs a write address and a write control signal in units of N frames to the dual port RAM to perform write control, and outputs phase information of an input timing pulse with respect to the control pulse; , input the phase information from this write control circuit and the determination pulse from the read control circuit,
A frame conversion circuit comprising: a determination circuit that determines the phase of the input timing pulse with respect to the control pulse to control the selection circuit.