JPH0212933A - Ceramic package for semiconductor integrated circuit - Google Patents

Ceramic package for semiconductor integrated circuit

Info

Publication number
JPH0212933A
JPH0212933A JP63164322A JP16432288A JPH0212933A JP H0212933 A JPH0212933 A JP H0212933A JP 63164322 A JP63164322 A JP 63164322A JP 16432288 A JP16432288 A JP 16432288A JP H0212933 A JPH0212933 A JP H0212933A
Authority
JP
Japan
Prior art keywords
integrated circuit
semiconductor integrated
bonding
wirings
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63164322A
Other languages
Japanese (ja)
Inventor
Nobuyuki Yamamichi
山道　信行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63164322A priority Critical patent/JPH0212933A/en
Publication of JPH0212933A publication Critical patent/JPH0212933A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H10W72/07141—Means for applying energy, e.g. ovens or lasers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07521—Aligning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To obtain a ceramic package in which wiring connection is conducted smoothly without contact with the ceramic body of a ceramic package during a bonding work by forming a surface so disposed as to have an oblique descending toward a semiconductor chip on the body. CONSTITUTION:Since the surface of the ceramic body 1 of a semiconductor integrated circuit device having wirings 8 has an oblique descending toward a semiconductor chip 2, in case of connecting bonding wirings 5 to the wirings 8, a stage for placing the body 1 is so inclined as to push a bonding tool 10 perpendicularly to the surface thereby to push the tool to the wirings 8, thereby connecting the wirings 5 thereto. In the case of connecting, the wirings 5 are extended perpendicularly to the surface of the chip 2, and even if the body 1 is inclined, it is not brought into contact with a metal sealing ring 4.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路のセラミックパッケージに関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a ceramic package for a semiconductor integrated circuit.

〔従来の技術〕[Conventional technology]

従来、セラミックパッケージは気密性に優れているので
、高信頼性の半導体集積回路のパッケージとして用いら
れてきた。Conventionally, ceramic packages have excellent airtightness and have been used as packages for highly reliable semiconductor integrated circuits.

第３図は従来の半導体集積回路装置の断面図を示す。こ
の装置のセラミック本体１は、グリーンシート法により
未焼結セラミックシートを複数枚製作し、それぞれの外
形を加工し、これらのシート面に金属ペーストをパター
ン印刷して配線８、外部リード６、半導体チップ２及び
金属シールリング４ａの固着用金属層をそれぞれに形成
し、それらセラミックシートを重ねて焼成し形成する。FIG. 3 shows a cross-sectional view of a conventional semiconductor integrated circuit device. The ceramic body 1 of this device is made by manufacturing a plurality of unsintered ceramic sheets using the green sheet method, processing the outer shape of each sheet, and printing a pattern of metal paste on the surface of these sheets to form wiring 8, external leads 6, and semiconductors. A metal layer for fixing the chip 2 and the metal seal ring 4a is formed respectively, and the ceramic sheets are stacked and fired.

また、パターン印刷で形成された配線及び固着用金属層
は焼成後に金めつき層で被覆される。このセラミック本
体１の中央の窪みには半導体チップ２が固着金属層には
んだ付けされている。更に、この半導体チップ２が搭載
された窪みの周囲を囲む平面に形成された配線８とこの
配線に対応する半導体チップ上の電極パッドとはワイヤ
ボンディング装置によりボンディングワイヤ５で接続さ
れている。外部回路と接続される外部リード６はセラミ
ック本体１の配線８の固着用金属層と連なる側面の固着
金属層にはんだ付けされている。蓋３は固着金属層に接
合された金属シールリング４でセラミック本体１に溶接
される。Further, the wiring and the metal layer for fixing formed by pattern printing are coated with a gold plating layer after firing. A semiconductor chip 2 is soldered to a fixed metal layer in the central recess of the ceramic body 1. Further, a wire 8 formed on a plane surrounding the recess in which the semiconductor chip 2 is mounted and an electrode pad on the semiconductor chip corresponding to this wire are connected by a bonding wire 5 using a wire bonding device. External leads 6 connected to an external circuit are soldered to the fixing metal layer on the side surface of the ceramic body 1 that is continuous with the fixing metal layer of the wiring 8. The lid 3 is welded to the ceramic body 1 with a metal sealing ring 4 joined to a fixed metal layer.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のセラミックパッケージは、半導体チップ
の電極パッドの面とセラミック本体を塞ぐ蓋の接合面と
の高さの差と、電極パッドと配線との水平方向の距離と
の比が大きく、このため製造上程々の問題が発生する。The conventional ceramic package described above has a large ratio between the height difference between the surface of the electrode pad of the semiconductor chip and the joint surface of the lid that closes the ceramic body, and the horizontal distance between the electrode pad and the wiring. Some manufacturing problems occur.

第４図はワイヤボンディング装置のボンディングツール
と半導体集積回路装置との相対位置を示す半導体集積回
路装置の部分断面図である。同図に示すように、この半
導体集積回路装置の半導体チップ２の電極パッド７とを
ボンディングワイヤ５で接続する際に、ボンディングワ
イヤ５が金属シールリング４の角部９に引掛かり、ボン
ディングワイヤ５がボンディングツール１０より抜ける
という問題がある。特に、ワイヤボンディング装置のボ
ンディングツールが超音波振動子と接続されている場合
は、ボンディングツールの先端にボンディングワイヤの
ボールを作らないので、ボンディングワイヤが抜けやす
い。このようにボンディングワイヤが抜けると、製造中
断になり多大な工数を浪費するという問題が起きる。FIG. 4 is a partial sectional view of the semiconductor integrated circuit device showing the relative positions of the bonding tool of the wire bonding device and the semiconductor integrated circuit device. As shown in the figure, when connecting the electrode pads 7 of the semiconductor chip 2 of this semiconductor integrated circuit device with the bonding wires 5, the bonding wires 5 catch on the corners 9 of the metal seal ring 4, and the bonding wires 5 There is a problem that the bonding tool 10 comes off. In particular, when the bonding tool of a wire bonding device is connected to an ultrasonic vibrator, the bonding wire is likely to come off because a ball of the bonding wire is not formed at the tip of the bonding tool. If the bonding wire comes off in this way, a problem arises in that production is interrupted and a large amount of man-hours are wasted.

本発明の目的は半導体チップの電極パッドとセラミック
本体の配線との接続が円滑に行われる構造を有する半導
体集積回路用セラミックパッケージを提供するこにある
。SUMMARY OF THE INVENTION An object of the present invention is to provide a ceramic package for a semiconductor integrated circuit having a structure that allows smooth connection between electrode pads of a semiconductor chip and wiring of a ceramic body.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体集積回路用セラミックパッケージは、半
導体集積回路が形成された半導体チップを載置する窪み
を有するとともに前記窪みの周囲を囲み前記半導体チッ
プの電極パッドと対応してボンディングワイヤで接続さ
れる配線が形成された第１の面と、前記第１の面を囲む
前記第１の面より高い第２の面に蓋を固着してなる半導
体集積回路用セラミックパッケージにおいて、前記第１
の面が前記半導体チップに向って降る傾斜面に形成され
たことを含んで構成される。The ceramic package for a semiconductor integrated circuit of the present invention has a recess on which a semiconductor chip on which a semiconductor integrated circuit is formed is placed, and the recess is surrounded by and connected to electrode pads of the semiconductor chip by bonding wires in correspondence with the electrode pads of the semiconductor chip. A ceramic package for a semiconductor integrated circuit comprising a lid fixed to a first surface on which wiring is formed and a second surface that surrounds the first surface and is higher than the first surface.
The surface of the semiconductor chip is formed as an inclined surface that slopes down toward the semiconductor chip.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の一実施例を示す半導体集積回路装置の
断面図、第２図はワイヤボンディング装置のボンディン
グツールと半導体集積回路装置との相対位置を示す半導
体集積回路装置の部分断面図である。この半導体集積回
路装置のセラミック本体１の配線８が設けられた面が半
導体チップ２に向って降る傾斜をもつように形成されて
いる。それ以外の構造は従来例と同じである。FIG. 1 is a cross-sectional view of a semiconductor integrated circuit device showing an embodiment of the present invention, and FIG. 2 is a partial cross-sectional view of the semiconductor integrated circuit device showing the relative positions of the bonding tool of a wire bonding device and the semiconductor integrated circuit device. be. The surface of the ceramic body 1 of this semiconductor integrated circuit device, on which the wiring 8 is provided, is formed to slope downward toward the semiconductor chip 2. The other structure is the same as the conventional example.

この構造にしたことにより、第２図に示すように、配線
が配置された面が傾斜をもっているので、配線８にボン
ディングワイヤ５を接続する際は、まず、ボンディング
ツール１０とこの面が垂直に押し付けられように、セラ
ミック本体１を積載するステージ（図示せず）を傾けて
、ボンディングツール１０を配線８に押し付はボングワ
イヤ５を接続する。この接続の際に、ボンディングワイ
ヤ５は半導体チップ２の面に対して垂直に張られていて
、このセラミック本体１を傾けるこにより、金属シール
リング４に接触することはない。また、半導体チップ２
の電極パッド７にボンディングワイヤ５を接続する場合
にも、電極パッド２と金属シールリング４とは十分かけ
離れているのでボンディングワイヤ５は金属シールリン
グ４に接触することはない。With this structure, as shown in FIG. 2, the surface on which the wiring is arranged has an inclination, so when connecting the bonding wire 5 to the wiring 8, first, the bonding tool 10 and this surface are perpendicular. A stage (not shown) on which the ceramic body 1 is mounted is tilted so that the bonding tool 10 is pressed against the wiring 8 to connect the bong wire 5. During this connection, the bonding wire 5 is stretched perpendicularly to the surface of the semiconductor chip 2, and by tilting the ceramic body 1, it does not come into contact with the metal seal ring 4. In addition, semiconductor chip 2
When connecting the bonding wire 5 to the electrode pad 7 , the bonding wire 5 does not come into contact with the metal seal ring 4 because the electrode pad 2 and the metal seal ring 4 are sufficiently far apart.

この実施例は配線を有する面が一段の場合について説明
したが、複数の階段の面をもつ場合でも同様にそれぞれ
の面に傾斜をもたせれば本発明の目的を得ることが出来
る。Although this embodiment has been described with reference to the case where the surface having wiring is one step, the object of the present invention can be achieved even in the case of having a plurality of step surfaces by similarly providing slopes to each surface.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、セラミックパッケージの
セラミック本体に、半導体チップに向って降る傾斜をも
つように配線が配置された面を形成したので、ワイヤボ
ンディング作業中にボンディングワイヤがセラミック本
体に接触することなく円滑に配線接続が出来る構造を有
する半導体集積回路用セラミックパッケージが得られる
という効果がある。As explained above, the present invention forms a surface on the ceramic body of a ceramic package on which wiring is arranged so as to slope downward toward the semiconductor chip, so that the bonding wire comes into contact with the ceramic body during the wire bonding operation. This has the effect of providing a ceramic package for semiconductor integrated circuits having a structure that allows smooth wiring connections without any damage.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例を示す半導体集積回路装置の
断面図、第２図はワイヤボンディング装置のボンディン
グツールと半導体集積回路装置との相対位置を示す半導
体集積回路装置の部分断面図、第３図は従来の半導体集
積回路装置の断面図、第４図はワイヤボンディング装置
のボンディングツールと半導体集積回路装置との相対位
置を示す半導体集積回路装置の部分断面図である。 １・・・セラミック本体、２・・・半導体チップ、３・
・・蓋、４・・・金属シールリング、５・・・ボンディ
ングワイヤ、６・・・外部リード、７・・・電極パッド
、８・・・配線、９・・・角部、１０．１０ａ・・・ボ
ンディングツール。FIG. 1 is a cross-sectional view of a semiconductor integrated circuit device showing an embodiment of the present invention, and FIG. 2 is a partial cross-sectional view of the semiconductor integrated circuit device showing the relative positions of the bonding tool of a wire bonding device and the semiconductor integrated circuit device. FIG. 3 is a sectional view of a conventional semiconductor integrated circuit device, and FIG. 4 is a partial sectional view of the semiconductor integrated circuit device showing the relative positions of the bonding tool of a wire bonding device and the semiconductor integrated circuit device. 1...Ceramic body, 2...Semiconductor chip, 3.
... Lid, 4... Metal seal ring, 5... Bonding wire, 6... External lead, 7... Electrode pad, 8... Wiring, 9... Corner, 10.10a.・Bonding tool.

Claims (1)

【特許請求の範囲】[Claims] 半導体集積回路が形成された半導体チップを載置する窪
みを有するとともに前記窪みの周囲を囲み前記半導体チ
ップの電極パッドと対応してボンディングワイヤで接続
される配線が形成された第１の面と、前記第１の面を囲
む前記第１の面より高い第２の面に蓋を固着してなる半
導体集積回路用セラミックパッケージにおいて、前記第
１の面が前記半導体チップに向って降る傾斜面に形成さ
れたことを特徴とする半導体集積回路用セラミックパッ
ケージ。a first surface having a recess for placing a semiconductor chip on which a semiconductor integrated circuit is formed, and on which wiring is formed surrounding the recess and connected to electrode pads of the semiconductor chip by bonding wires; In a ceramic package for a semiconductor integrated circuit in which a lid is fixed to a second surface that surrounds the first surface and is higher than the first surface, the first surface is formed as an inclined surface that slopes down toward the semiconductor chip. A ceramic package for semiconductor integrated circuits characterized by:
JP63164322A 1988-06-30 1988-06-30 Ceramic package for semiconductor integrated circuit Pending JPH0212933A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63164322A JPH0212933A (en) 1988-06-30 1988-06-30 Ceramic package for semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63164322A JPH0212933A (en) 1988-06-30 1988-06-30 Ceramic package for semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH0212933A true JPH0212933A (en) 1990-01-17

Family

ID=15790957

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63164322A Pending JPH0212933A (en) 1988-06-30 1988-06-30 Ceramic package for semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH0212933A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996003020A1 (en) * 1994-07-19 1996-02-01 Olin Corporation Integrally bumped electronic package components
US9406576B2 (en) 2012-11-19 2016-08-02 Fuji Electric Co., Ltd. Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996003020A1 (en) * 1994-07-19 1996-02-01 Olin Corporation Integrally bumped electronic package components
US5629835A (en) * 1994-07-19 1997-05-13 Olin Corporation Metal ball grid array package with improved thermal conductivity
US9406576B2 (en) 2012-11-19 2016-08-02 Fuji Electric Co., Ltd. Semiconductor device
JP6024759B2 (en) * 2012-11-19 2016-11-16 富士電機株式会社 Semiconductor device

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