JPH02129751A - Bus use controller - Google Patents

Abstract

PURPOSE:To improve the processing speed of the whole device by constituting a bus use controller so that the bus use priority of data processors becomes in the descending order of bus use frequency. CONSTITUTION:A bus use monitoring circuit 6 counts up the number of times of significancy in n bus acknowledge signals ACK1 to ACKn in each fixed time and a priority determining circuit 7 determines the priority order of data processors in the descending order of count values and outputs a priority state signal 8 indicating the priority order. Thereby, the highest priority order can be always applied to the data processor with the highest using frequency and the bus use waiting time can be shortened. Thus, the processing speed of the whole device can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bus commentary control device for controlling the use of buses of a plurality of day and evening processing devices connected to the same bus.

[Conventional technology]

FIG. 2 is a diagram showing an example of a conventional bus usage control device.

In the figure, (1) is a bus arbitration circuit, (2) is a bus request signal that indicates whether each data processing device is requested to use the bus, and (3) is a bus that allows each data processing device to use the bus. This is a permission signal. (4) is an arbitration timing signal.

Next, the operation will be explained. In fig.

The bus request signal (2) is connected to n data processing devices, and each data processing device makes the bus request signal (2) t-significant when data processing using the bus occurs. The bus arbitration circuit (1) uses one of the bus request signals (2) for arbitration when multiple bus requests occur simultaneously.
Give priority to each book. In this example, REQI, R
EQ2. = , the priority is high in the order of REQnO.

FIG. 3 is a timing diagram showing the operation of the bus arbitration circuit (1). At the rising edge of the arbitration timing signal, the bus arbitration circuit (1) determines whether the bus will be used by the device with the highest priority among the data processing devices that have requested the bus.
e, and makes the corresponding bus grant signal (3) significant. Here, the bus request with the highest priority at time A is REQ
k, and on the other hand, the bus arbitration circuit makes the bus grant signal ACKk significant. As a result, the second data processing device is allowed to use the bus.

[Problem to be solved by the invention]

Since the conventional bus conversion control device is configured as 9 or more, the data processing device with low priority is.

Even if a bus usage request is issued, if there are higher bus usage demands from data processing devices, it is necessary to wait until those bus usage demands disappear. Therefore, if a data processing device that frequently generates bus requests is placed at a low priority, the latency of that data processing device will increase.

Furthermore, if there are a large number of data processing devices that wait for the processing results of the data processing devices with lower priority before operating, there is a problem in that the processing speed of the entire device will be reduced.

This invention was made to solve the above-mentioned problems.It monitors the frequency of bus requests and adds a function to change the priority order of data processing devices. It is an object of the present invention to provide a bus usage control device which can reduce bus usage waiting time and further improve the processing speed of the entire device.

[Means to solve the problem]

The bus usage control device according to the present invention is provided with the following means.

(a) Means for monitoring the bus usage status of a plurality of devices that share the bus for each device.

(b) Means for prioritizing each device based on predetermined criteria from the bus usage status of each device.

(C) When bus use requests from various devices conflict.

A means of selecting bus usage based on this priority.

[Effect]

The bus usage control device according to the present invention monitors the bus usage status of each data processing device and sets the bus usage priority order of the data processing devices based on a predetermined criterion such as the order of bus usage frequency.

To reduce the waiting time when using a bus in a data processing device that uses the bus frequently, and to improve the processing speed of the entire device.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, parts indicated by the same reference numerals as in Fig. 2 are the same.
Or a considerable portion.

(5) is a priority generation circuit, which consists of a bus usage monitoring circuit (61) and a priority determination circuit (7).(8)
is a priority status signal indicating the bus usage priority of each data processing device.

Next, the operation will be explained. n data processing devices are connected to the bus, and the use of the bus by these plurality of data processing devices is based on n buses that are output from each data processing device and input to the bus arbitration circuit (1). Request signal REQ1. ..., REQn, and bus arbitration circuit (1)
n bus permission signals ACK1° . The bus arbitration circuit is given a priority order for the n bus request signals by a priority status signal (8), and performs an arbitration operation based on this priority order. The priority generation circuit (5) is.

It consists of a bus usage monitoring circuit (6) and a priority order determining circuit (7), which determines the priority order of the bus based on the frequency of use of the bus.

In other words, the bus usage monitoring circuit (6)
Actual bus permission signal ACK1. ... , counts the number of times that ACKnK becomes significant, and calculates n count values (count value 1... , count value n) f: Priority determination circuit (7)
Output to. The priority determination circuit has a count value of 1,...
, the count value n are compared, and priority is given to the data processing devices in descending order of the count value, that is, in order of bus usage frequency, and a priority status signal (8) indicating the priority is output. As a result, it is possible to always give high priority to data processing devices that are used frequently, and it is possible to reduce the bus usage waiting time of data processing devices that use the bus frequently.

It becomes possible to improve the processing speed of the entire device.

In the above practical example, the bus usage monitoring circuit counts the number of bus usages that occur within a certain period of time, but it may also monitor the time interval from the generation of a bus request to the generation of the next bus request. good.

Further, although the priority order determination circuit has been designed to give a higher priority to the items that are used more frequently, it is not necessarily necessary to give a higher priority to the items that are used more frequently.

It does not matter if priority is given in terms of speed change.

〔Effect of the invention〕

As described above, according to the present invention, the bus usage control device is configured to control the bus usage priority of the data processing device.

Since the bus is arranged in a predetermined order, such as the most frequently used bus, it is possible to eliminate the waiting time when using the bus for data processing devices that use the bus frequently, increasing the processing speed of the entire device. It has the effect of improving the

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram of a bus usage control device according to an embodiment of the present invention, FIG. 2 is a block configuration diagram of a conventional bus usage control device, and FIG. 3 is an operation of a conventional 4-bus bus control device. FIG. (1) is a bus arbitration circuit, (2) is a bus request signal, (3)
is the bus permission signal, (4) is the arbitration timing signal, and (5)
is a priority generation circuit, (6) is a bus usage monitoring circuit, and (7) is a priority generation circuit.
) is a priority determination circuit, and (8) is a priority status signal. Note that in FIG. 9, the same reference numerals indicate the same or complementary parts.

Claims (1)

[Claims] A bus usage control device having the following means: (a) means for monitoring the bus usage status of a plurality of devices that share the bus for each device; (b) monitoring the bus usage status of each device; , means for prioritizing each device based on predetermined criteria; (c) selecting a device to use the bus based on the priority order when bus use requests from each device conflict; means.