JPH02129961A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor integrated circuit device, and particularly to a technique that is effective when applied to a semiconductor integrated circuit device having a memory function.

[Conventional technology]

E E P ROM (E electrically programmable Rea
d0nly Memory) non-volatility and DRAM
(Dynamic Random access M
A non-volatile RAM has been developed that also has the high speed of memory.

Regarding this developed technology, for example, 1987 Symposium on VLSI Circuit Paper No. IV-5 (1987Sy+Wposium on VL
SI C1rcuits, IV-5, May 198
7).

The memory cells of the non-volatile RAM are F of the EEPROM.
A DRAM memory cell is combined with a LOT OX (Floating Gate Internal Oxide) type memory cell.

The FLOTOX type memory cell is constituted by a series circuit of a field effect transistor having a small memory cell gate electrode and a control gate electrode, and a cell selection field effect transistor. In other words, it has a FLOTOX type memory cell transistor structure with a small number of memory cells. The latter cell selection field effect transistor is connected in series to one semiconductor region of the former field effect transistor. One semiconductor region of the field effect transistor extends to the bottom of the information storage gate electrode, and a tunnel oxide film is interposed between the one semiconductor region and the information storage gate electrode. The other semiconductor region of the field effect transistor is connected in series with a mode switching field effect transistor for switching between EEPROM function and DRAM function.

The memory cell of the DRAM is constituted by a series circuit of an information storage capacitor element and a cell selection field effect transistor. The capacitive element for information storage is a semiconductor region (one electrode)
It has a planar structure in which a dielectric film and a plate electrode (the other electrode) are sequentially laminated thereon. The plate electrode (the other electrode) of the information storage capacitive element is the FLOT
The OX type memory cell is formed integrally with and electrically connected to the control gate electrode of the small memory cell transistor. In addition, the semiconductor region (one electrode) of the information storage capacitive element is F
The LOTOX type memory cell is formed integrally with one semiconductor region of the small memory cell transistor and is electrically connected thereto. That is, one memory cell that holds 1 bit of information in the nonvolatile RAM is composed of four field effect transistors and one information storage capacitive element.

Non-volatile RAM configured in this way has DR during operation.
It is used as an AM, and has the feature that it can be used as an EEPROM during standby when the power supply is cut off due to a power outage or the like. Also, this non-volatile RAM.

Since DRAM is used, which has a smaller memory cell area than S RAM (Static RAM), it has the feature that the area occupied by the memory cell can be reduced and higher integration can be achieved.

The operation of transferring data from a DRAM memory cell to a FLOTOX type memory cell is performed by applying a high voltage to the control gate electrode and injecting electrons from one semiconductor region to the information storage gate electrode through the tunnel oxide film. There is. Further, the information writing operation is performed by applying a high voltage to the one semiconductor region and extracting electrons from the information storage gate electrode to the one semiconductor region through the tunnel oxide film. This mode switching is performed by the mode switching field effect transistor, and the high voltage used is about 17 to 20 [V].

[Problem to be solved by the invention]

In the non-volatile RAM described above, the memory cell is composed of a total of four field effect transistors and one information storage capacitive element, so there is a limit to reducing the area occupied by the memory cell, and the degree of integration must be improved. The problem was that it could not be done.

In addition, when the nonvolatile RAM is loaded into a FLOTOX type memory cell from a DRAM memory cell, the FLOTOX type memory cell is
A high electric field is generated between the control gate electrode of the OTOX type memory cell transistor and one semiconductor region. In other words, the dielectric film of the information storage capacitive element has 5 [MV/
Since a high electric field of approximately AAL is applied and a thick dielectric film of approximately 340 to 400 [people] is required, the area occupied by the information storage capacitive element must be increased in order to obtain the specified amount of charge storage. It won't happen. For this reason, nonvolatile RAMs have a problem in that the degree of integration cannot be improved because there is a limit to reducing the area occupied by the memory cells.

An object of the present invention is to provide a technique that can improve the degree of integration of a semiconductor integrated circuit device having a nonvolatile RAM.

Another object of the present invention is to provide a technique capable of achieving the above object by reducing the number of transistors in the memory cell of the nonvolatile RAM and reducing the area occupied by the information storage capacitor element of the DRAM. It's about doing.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of one typical invention disclosed in this application is as follows.

Non-volatile RAM that combines EEPROM and DRAM
In the semiconductor integrated circuit device having the nonvolatile R
The non-volatile memory cell of the EEPROM of the AM memory cell is configured as a flash type (one transistor structure).

[For production]

According to the above-mentioned means, the flash type nonvolatile memory cell has a one-transistor structure, and the area occupied by the memory cell of the nonvolatile RAM can be reduced by an amount equivalent to a cell selection field effect transistor, and the area occupied by the memory cell of the nonvolatile RAM can be reduced. Flash-type nonvolatile memory cells can reduce the information write voltage, and the dielectric film of the information storage capacitor can be made thinner to increase the amount of charge storage and reduce the area occupied by the information storage capacitor. However, since the area occupied by the memory cells of the nonvolatile RAM can be reduced, the degree of integration of the semiconductor integrated circuit device can be improved. In other words, by adopting a flash-type nonvolatile memory cell, a nonvolatile RAM memory cell can be configured with three field effect transistors and one information storage capacitive element, which reduces the integration density of a semiconductor integrated circuit device. can be improved.

Hereinafter, the configuration of the present invention will be explained along with one embodiment.

Note that throughout the description of the embodiments, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiments of the invention]

FIG. 1 (equivalent circuit diagram) shows the structure of a memory cell of a nonvolatile RAM which is an embodiment of the present invention.

As shown in Figure 1, 1 [bit] of non-volatile RAM
The memory cell M that forms the information is a nonvolatile memory cell Ml! of EEPROM. and a DRAM memory cell M0 are combined.

The nonvolatile memory cell M9 of the EEFROM is composed of a field effect transistor Q having an information storage gate electrode (floating gate electrode) and a control gate electrode (control gate electrode). In other words, the nonvolatile memory cell M5 is of a flash type, that is, has a one-transistor structure. The field effect transistor Q is constructed of an n-channel type.

A control gate electrode of a field effect transistor Q2 of the nonvolatile memory cell M1 is connected to a data line DL2 through a cell selection field effect transistor Q1 of a DRAM, which will be described later. One semiconductor region (source region) of the field effect transistor Q is connected to a reference potential, for example, a circuit ground potential of 0 [V]. Field effect transistor Q
, the other semiconductor region (drain region) is connected to the data line DLL with a mode switching field effect transistor Q interposed therebetween.
It is connected to the. This mode switching field effect transistor Q is constructed of an n-channel type, and has a gate electrode connected to the mode switching signal line ML.

The memory cell MI) of the DRAM is constituted by a series circuit of a cell selection field effect transistor Q8 and an information storage capacitive element C. One semiconductor region of the cell selection field effect transistor Q8 is connected to the data line DL2, and the other semiconductor region is connected to one electrode of the information storage capacitive element C and the control gate electrode of the field effect transistor Q. It is connected to the. The gate electrode of this cell selection field effect transistor Q is connected to the word line WL. The other electrode of the information storage capacitive element C is connected to one semiconductor region of the field effect transistor Q2.

The data lines DLL and DL2 are spaced apart from each other and extend in the same column direction. The word line WL.

Each of the mode switching signal lines ML extends in the same row direction.

Next, the specific structure of the main part of the memory cell of the nonvolatile RAM will be briefly explained using FIG. 3 (a sectional view of the main part).

As shown in FIG. 3, the memory cell M of the nonvolatile RAM is formed on the main surface of a p-type semiconductor substrate (or a well region formed on the main surface) made of single crystal silicon. In reality, each element of the memory cell M is surrounded by an element isolation insulating film and is electrically isolated from other elements, but this isolation structure is omitted in FIG. 3 for a simplified illustration.

Among the memory cells M, the nonvolatile memory cell M5 of the EEPROM is constituted by the field effect transistor Q as described above. That is, the field effect transistor Q mainly consists of a semiconductor substrate 1. Gate insulating film 2, gate electrode for information storage 3. Gate insulating film 5. It is composed of a control gate electrode 6 and a pair of n-type semiconductor regions 4 which are a source region and a drain region. Each of the gate insulating films 2 and S is formed of, for example, a silicon oxide film, and the information storage gate electrode 3 is formed of, for example, a polycrystalline silicon film. The control gate electrode 6 is formed of, for example, a single layer of a polycrystalline silicon film, a high melting point metal film, a high melting point metal silicide film, or a composite film thereof.

A wiring 9 is connected to one n-type semiconductor region 4 of the field effect transistor Q2. Wiring 9.

It extends over the interlayer insulating film 7 and is connected to one n-type semiconductor region 4 through a connection hole 8 formed in the first interlayer insulating film 7 . The wiring 9 is formed of, for example, an aluminum alloy film.

The mode switching field effect transistor Q mainly consists of a semiconductor substrate 1. Gate insulating film 2. It is composed of a gate electrode 3 and a pair of n-type semiconductor regions 4 which are a source region and a drain region. In the mode switching field effect transistor Q, one n-type semiconductor region 4 is the field effect transistor Q,
The other n-type semiconductor region 4 is connected to the wiring (data line DLL) 9 .

Although not shown in FIG. 3, the cell selection field effect transistor Q of the memory cell M0 of the DRAM has substantially the same structure as the mode switching field effect transistor Q. Data line DL2 is formed of wiring 9.

The information storage capacitive element C of the memory cell M has an n-type semiconductor region (one electrode)4. It has a planar structure in which a dielectric film 5 and a plate electrode (the other electrode) 6 are sequentially laminated. This n-type semiconductor region 4 is constructed integrally with one n-type semiconductor region 4 of the field effect transistor Q, and the plate electrode 6 is constructed integrally with the control gate electrode 6 of the field effect transistor Q.

Next, the operation of the nonvolatile RAM configured as described above will be briefly explained using FIG. 1.

(During operation) When the nonvolatile RAM is in operation, the mode switching signal line ML
is held at a low level (eg, O[V]).

As a result, the mode switching field effect transistor Q of the memory cell M is maintained in a non-conductive state, and the memory cell M is used as a DRAM as shown in FIG. 2 (equivalent circuit diagram in DRAM mode).

(Standby) When the power is cut off due to a power outage, etc., the DRAM memory cell M
This information write operation, in which the information held in I, is written to the nonvolatile memory cell M6 of the EEPROM, first sets the word line WL to a high level and turns on the cell selection field effect transistor Q1 of the memory cell M0. The information held in the information storage capacitive element C is transferred to the data line DL2.
The signal is latched by a sense amplifier circuit (not shown) via the signal.

(1) When the information held in the information storage capacitive element C is at a low level, a high voltage is applied to the data line DL1, and the mode switching field effect transistor Q is activated.

is made conductive, the other n-type semiconductor region (drain region) 4 of the field effect transistor Q2 of the nonvolatile memory cell M9 is held at a high voltage, and a low voltage is applied to the data line DL2. The control gate electrode 6 of the field effect transistor Q of the nonvolatile memory cell M1 is maintained at a low level by turning on the transistor Q. As a result, electrons from the information storage gate electrode 3 of the field effect transistor Q of the nonvolatile memory cell M6 are extracted to the n-type semiconductor region 4. As the high voltage, for example, 13 to 15 [:V] is used, and as the low voltage, 0 [V] is used. The electron extraction is Fowlar-Nord
This is done using a heim current (tunneling phenomenon).

(2) When the information held in the information storage capacitive element C is at a high level, a high voltage is applied to the data line DLL, and the field effect transistor Q for mode switching is activated.

conductive state and the other n-type semiconductor region (drain region) of the field effect transistor Q of the nonvolatile memory cell M2.
4 is held at a high voltage, and at the same time, a high voltage is applied to the data line DL2, and the cell selection field effect transistor Q is made conductive to control the control gate electrode 6 of the field effect transistor Q of the nonvolatile memory cell ME. Hold at a high level.

As a result, electrons are injected into the information storage gate electrode 3 of the field effect transistor Q of the nonvolatile memory cell Mg. The high voltage is similar to the above value. The injection of electrons is performed in the other n-type semiconductor region (
This is carried out using an avalanche current (hot electron phenomenon) due to a high electric field generated near the drain region (drain region) 4.

Next, when the aforementioned power cutoff is avoided, the information held in the nonvolatile memory cell M6 is transferred to the memory cell M of the DRAM.
This information write operation of writing to 0 first begins with the data line D.
L1. Precharge each of DL2 and memory cell M0.
The cell selection field effect transistor Q8 and the mode switching field effect transistor Q are kept conductive. For example, 5 [V] is used as the precharge voltage.

(1) When electrons are extracted from the information storage gate electrode 3 of the field effect transistor Q of the nonvolatile memory cell M, the field effect transistor Q becomes conductive, and the potential of the data line DLI decreases. However, the n-channel field effect transistor Q provided on the data line DL2 becomes non-conductive.

As a result, the potential of the data line DL2 decreases, and the DRAM
The information storage capacitive element C of the memory cell M retains low level information.

(2) When electrons are injected into the information storage gate electrode 3 of the field effect transistor Q of the nonvolatile memory cell M8, the field effect transistor Q2 becomes non-conductive, and the potential of the data line DLL is precharged. It is held at a potential, and field effect transistor Q of data line DL2 becomes conductive. As a result, the potential of the data line DL2 is held at the precharge potential, and high level information is held in the information storage capacitive element C of the memory cell M0 of the DRAM.

The field effect transistor Q provided on the data line DL2 is not provided for each memory cell M, but one for each plurality of memory cells.

Next, a method for manufacturing the memory cell M of the nonvolatile RAM will be briefly described using FIGS. 4 and 5 (cross-sectional views of main parts shown for each manufacturing process).

First, gate insulating film 2 is formed on the main surface of p-type semiconductor substrate 1 made of single crystal silicon. The gate insulating film 2 is formed of, for example, a silicon oxide film obtained by oxidizing the main surface of the semiconductor substrate 1.

Next, as shown in FIG. 4, a gate electrode 3 is formed on the gate insulating film 2. The gate electrode 3 is formed as an information storage gate electrode 3 in the region where the nonvolatile memory cell Me is formed.

Next, as shown in FIG. 5, n-type impurities are introduced into a predetermined main surface portion of the semiconductor substrate 1 to form an n-type semiconductor region 4. The n-type impurity is introduced into the main surface of the semiconductor substrate 1 through the gate insulating film 3 by ion implantation using the gate electrode 3 as a mask for impurity introduction. By this step of forming the n-type semiconductor region 4, the mode switching field effect transistor Q of the memory cell M and the cell selection field effect transistor Q of the memory cell M0 (not shown) are completed.

Next, a gate insulating film 5. Each dielectric film 5 is formed on the main surface of the n-type semiconductor region 4 in the formation region of the memory cell M0.

Next, as shown in FIG. 6, a control gate electrode 6. Plate electrodes 6 are formed on top of dielectric film 5 . By forming the control gate electrode 6, the field effect transistor Q of the nonvolatile memory cell M8 is completed. Further, the plate electrode 6
By forming the information storage capacitive element C, the information storage capacitive element C is completed.

Next, interlayer insulating film 7. By sequentially forming the connection hole 8 and the wiring 9, the memory cell M of the nonvolatile RAM shown in FIG. 1 is completed.

In this way, DR is applied to nonvolatile memory cells of EEFROM.
In a semiconductor integrated circuit device having a nonvolatile RAM formed by a memory cell that is a combination of AM memory cells,
A field effect transistor Q in which the memory cell M of the nonvolatile RAM has an information storage gate electrode 3 and a control gate electrode 6.

a flash type nonvolatile memory cell M formed of;
The plate electrode 6 and source region (
An information storage capacitive element C formed by an electrode connected to the n-type semiconductor region 4) and a cell selection field effect transistor Q
, which series circuit forms the memory cell M0 and the drain region (n
4), and a mode switching field effect transistor Q connected in series to the type semiconductor region 4). With this configuration, the flash type nonvolatile memory cell Mg has a one-transistor structure, which corresponds to the field effect transistor for cell selection of the conventional FLOTOX type nonvolatile type upper volatile memory cell register structure). The area occupied by the memory cell M can be reduced, and the flash type nonvolatile memory cell ME can reduce the information write voltage by approximately 2 to 7 [V], and the information storage capacitive element C The dielectric film 5 of the semiconductor integrated circuit can be made thinner to increase the amount of charge storage, reduce the area occupied by the information storage capacitive element C, and reduce the area occupied by the memory cell M of the nonvolatile RAM. The degree of integration of the device can be improved.

In other words, the memory cell M of the nonvolatile RAM is a flash type nonvolatile memory cell M2.

Since it can be configured with three field effect transistors (Q, , Q, , Q,) and one information storage capacitive element C, the degree of integration of the semiconductor integrated circuit device can be improved.

Furthermore, since the field effect transistor Q of the nonvolatile memory cell M1 does not require a region for forming a tunnel oxide film unlike the field effect transistor of the FLOTOX type memory cell, the memory cell of the nonvolatile RAM Reduce the area occupied.

It is possible to improve the degree of integration of semiconductor integrated circuit devices.

The invention made by the present inventor has been specifically explained above based on the above embodiments, but the present invention &

It goes without saying that the invention is not limited to the embodiments described above, and that various changes can be made without departing from the spirit thereof.

For example, in one aspect of the present invention, each field effect transistor constituting the memory cell M is connected to an LDD (Lightly D
(oped drain) structure).

(Effects of the Invention) The effects obtained by typical inventions disclosed in this application will be briefly explained (4) as follows.

The degree of integration of a semiconductor integrated circuit device having a nonvolatile RAM can be improved.

[Brief explanation of the drawing]

FIG. 1 is an equivalent circuit diagram showing the configuration of a memory cell of a nonvolatile RAM according to an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of the memory cell in DRAM mode. FIG. 3 is a cross-sectional view of the main part of the memory cell in FIGS. 4 to 6.
The figure is a sectional view of a main part of a memory cell shown for each manufacturing process. In the figure, 2, 5...gate insulating film or dielectric film, 3...
- Gate electrode or gate electrode for information storage, 4... n-type semiconductor region, 6... gate electrode or plate electrode for control, M... memory cell, Q... field effect transistor, C... Information storage capacitive element, DL: data line, WL: word line.

Claims (1)

[Scope of Claims] 1. In a semiconductor integrated circuit device having a non-volatile RAM formed by a memory cell in which a non-volatile memory cell of an EEPROM is combined with a memory cell of a DRAM, the memory cell of the non-volatile RAM stores information. A flash type nonvolatile memory cell formed of a field effect transistor having a storage gate electrode and a control gate electrode, an electrode connected to the control gate electrode of the flash type nonvolatile memory cell, and a source region connected to the flash type nonvolatile memory cell. A memory cell formed by a series circuit of an information storage capacitive element formed by an electrode and a cell selection field effect transistor, and a mode switching field effect connected in series to the drain region of the flash type nonvolatile memory cell. A semiconductor integrated circuit device comprising a transistor. 2. The memory cells of the non-volatile RAM have DR during operation.
2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is used as an AM, and used as an EEPROM during standby.