JPH0213397B2 - - Google Patents

Description

[Detailed description of the invention]

[Field of Application of the Invention] The present invention relates to a self-gate AND circuit (hereinafter referred to as SGA) used in a latch circuit in an AC-driven Josephson logic circuit. [Prior art] In an AC-driven Josephson logic circuit,
A latch circuit is required to carry over the calculation results from one power cycle to the next cycle. The latch circuit includes a master flip-flop that holds data during transitions of the AC power supply;
It consists of a slave flip-flop that holds data during the steady state portion of the AC power supply. Among these, the master flip-flop is a DC-driven flip-flop circuit or a Josephson magnetic quantum interferometer (JI).
A storage loop, which is a superconducting loop consisting of an inductance and an inductance, is used. In addition, the slave flip-flop reads the data of the master flip-flop at the beginning of an AC power cycle, holds the logic output of the dual rail corresponding to that data for the next cycle, and provides its output to the logic output network of . During this one cycle, even if the data in the master flip-flop changes, the data in the slave flip-flop does not change. literature,
A. Davidson, “A Josephson Latch”, IEEE
Journal of Solid State Circuits, vol., SC−
13, No. 5, October 1978, pp. 583-590 (hereinafter referred to as Document 1), such a latch circuit is explained in detail. Document 1 discloses, as a slave flip-flop, a circuit called a self-gate AND (SGA) in which two AND gates are cross-coupled as shown in FIG.
In FIG. 1, 11 and 12 are ADN gates,
15, 16 are positive outputs of these gates, 17,
18 is a negative output (NAND). 13,14
are the truth (T) and complementary (C) inputs to each SGA circuit.
15 and 16 are true output T ^* and supplementary output C ^* respectively
It is. AND gates 11 and 12 have a latching property in an AC drive logic circuit system, so once the AND gates 11 and 12
If the switch is switched and the T ^* output is generated, the operation of the 12 is suppressed, and even if the C input occurs thereafter, the 12 cannot be switched. Therefore, if the SGA reads a T or C input at the beginning of an AC power cycle, the SGA will hold a constant T ^* or C ^* during that cycle. However, a finite amount of time is required from when the SGA starts reading data from T or C until it determines the output from T ^* or C ^* (referred to as locking), and during this time, the master flip-flop The state of the tap shall not change. Therefore, the locking time is short.
It is one of the important indicators of SGA performance. Literature 1
The structure of the circuit used as an AND gate in the SGA is shown in Figures 2a and 2b. Figure 2a
, AND gate 11 has inputs 13 and 1
9 and generates a positive output 15 and a negative output 17. Specifically, as shown in FIG. 2b, the JI 31 is supplied with power from the power supply bus 20 via the resistor 23,
JI3 is powered from the output of JI31 via resistor 21
It consists of 2. JIs 31 and 32 receive inputs 13 and 19, respectively. The output current flowing from JI32 to resistor 22 is positive output 1 of AND gate 11.
5. The current flowing from JI 31 to ground is negative output 17. The structures of JI31 and JI32 described above are shown in FIG. 2c. In the figure, 33 is a Josephson junction, 29 is a shunt resistor, the wiring from 27 to 28 is an input signal line, and 30 is a mutual inductance. 1
7 is when using AND gate 11 alone.
Although it will not be a NAND output, if it is used as an SGA as shown in Figure 1 and inputs 13 and 14 are always exclusive events, it will become a NAND output. The overall circuit configuration of the above-mentioned SGA is as shown in FIG. In the figure, JI's Q ₁ 44
and Q ₃ 46 constitute 11 AND gates 11, which have inputs 13 and 18, and a positive output 15 and a negative output 17. Also, JI's Q ₂ 45 and Q ₄ 4
7 constitutes another AND gate 12, and 14
and 17 as inputs, positive output 16, negative output 18
has. In the figure, 40 is a power supply bus, 41 is a shunt resistor, and 42 and 43 are load resistors. Above Q ₁ 4
4 and Q ₃ 46 are gates for reading out data from the master flip-flop, and will hereinafter be collectively referred to as detection stage gates for the sake of explanation. On the other hand, Q ₂ 45 and Q ₄
Since 47 is a gate that outputs data to the subsequent logic circuit network, it is hereinafter referred to as an output stage gate for the sake of explanation. The SGA in Figure 3 is of a type that receives complementary signals of True and Complementary from the master flip-flop, but it receives the presence or absence of current in the storage loop as single-rail data of "1" and "0". There are also formats. Such SGAs include those based on the logic shown in Figure 4a, and
There is a method that uses a reference output ref52 as shown in FIG. 4b. Both receive data input 51 to be identified and generate outputs True 53 and Complementary 54. An example of the method shown in Figure 4a is F.
Tsui and CPWang, “SGA with Single−Rail
Data Input”, IBM Technical Disclosure
Bulletin, vol.21, No.12, May 1979, pp5055~
5057 (Document 2) discloses the circuit shown in FIG. On the other hand, the method shown in Figure 4b is A.
Davidson and H.C. Jones, “Josephson
Comparator SGA for Use with Data
“Latches”, IBM Technical Disclosure
Bulletin, vol.23No.4, September 1980, pp1690
1693 (Document 3) discloses the circuit shown in FIG. In FIG. 5, 60 is a power supply bus, 61
is a shunt resistance, and 64 to 67 are JI. Also, the 6th
In the figure, 70 is a power supply bus, 71 is a shunt resistor,
72 is a load resistor, 73 is JI, and 74 to 76 are single Josephson junctions. Also, as another example of the method shown in Figure 4b, HC Jones, “Self-Resetting
AC Powered Latch”, IBM Technical
Disclosure Bulletin, vol.23, No.9, February
1981, p4348 (Reference 4) discloses the circuit shown in FIG. In the figure, 80 is a power bus, 81 is a shunt resistor, 82 is a load resistor, 83 is JI, and 84 is
CIL (Current Injection Logic), 85 is a Josephson junction. CIL is used to amplify outputs 53 and 54. The driving ability of the next-stage logic circuit network of the SGA is also an important property, and it is important to be able to obtain a large output. In general, in an SGA, configuring the output stage with an injection type gate rather than a magnetic flux coupling type is effective in achieving high-speed locking and increasing output. . References, A. Davidson,
“Self-Gating And for Current Injection
Logic”, IBM Technical Disclosure Bulletin,
vol.21, No.1, June 1978, pp421-422 (Reference 5)
In this case, the output stages JI46 and 47 of the circuit shown in Fig. 3 are connected to CIL.
A circuit like that shown in FIG. 8 is shown in which . In the figure, 100 is a power supply bus, 101 is a shunt resistor, 102 is a load resistor, and 103 and 104 are
JI, 105, 106 are CIL. Although the output current of this circuit is certainly greater than that of FIG. 3, there are significant drawbacks. That is, once Q ₁ 103,10
Even if Q ₂ 104 switches after that, Q ₄ 106 must not turn on.
That is, after the T ^* output is established, the C ^* output must be disabled. However, injection gates such as CIL do not have input/output isolation, and Q ₃
When 105 switches, the gate current of Q ₄ 106 increases. Malfunctions are more likely to occur.
Also, the SGA in Figure 3, which is composed of four JIs,
It is easy to think of adding two CILs to configuring an SGA as shown in Fig. 9 or 10 from the example shown in Fig. 7, but in the same way, the output current is Although large, there is a drawback that the C(T) output operation disable mechanism after the T(C) output is turned on is uncertain. [Object of the invention] The object of the invention is to
An object of the present invention is to provide an SGA circuit that increases the output current amplitude without making the operation disable mechanism unstable. [Summary of the Invention] The present invention does not use injection type logic gates that do not have input/output separation like conventional CIL.
By using a gate with a large output current amplitude, the reliability of the C(T) operation disable mechanism after the T(C) output is turned on is maintained. [Examples of the Invention] Hereinafter, the present invention will be described in detail with reference to Examples. In the following explanation, a quantitative discussion will be made assuming that the Josephson junction has a critical current density of 1000 A/cm ² and that the junction area of the Josephson junction 33 shown in Figure 2 c, which is the basis of the configuration, is 5 μmφ. However, the present invention is of course not limited to these values. Further, other numerical values in FIG. 2c and FIG. 7b are as follows. That is, 34 is two Josephson junctions 33 arranged in a row, 95 is three similarly arranged in a row, 35 is an inductance of 1.5 PH, 96 is an inductance of 2.4 PH, 97 is an inductance of 0.8 PH, and 36 and 98 are 2 Ω inductances. It is used as a damping resistance. Also, 61 shown in Figure 8 is 20Ω,
62 is 3Ω, 101 shown in Figure 8 is 20Ω, 10
2 is 2.5Ω. These circuits are HCWard
Huang et al., “High−Reliability Pb−Alloy
Josephson Junction for Integrated Circuits”
IEEE Trans.on Electron Devices, vol.ED−
27, No. 10, October 1980, pp 1979-1987 (Reference 6). Example 1: FIG. 11a shows an SGA that is an embodiment of the present invention. In the figure, 130 is a power supply bus, 131 is a 20Ω shunt resistor, and 132 is a 100Ω shunt resistor.
Ω shunt resistance, 133 is 3Ω load resistance, Q ₁ 1
34, Q ₂ 135, Q ₃ 136, and Q ₄ 137 are JI shown in FIG. 2c. When the T input 13 is "1" (current value 0.4 mA) and the C input 14 is "0" (current value 0 mA), after increasing the power supply voltage from 0 mV to 11.2 mV with a rise time of 100 ps,
Let's keep it constant at 11.2mV. First, Q ₁ switches, then Q ₃ switches. Output current ^* 1
The steady-state value of 5 is 0.38 mA, and the simulation shows that it reaches its 90% value at time 201 ps. Here, for the parasitic inductance of the wiring in the circuit, the value when fabricated using the technique of Document 6 was used. The corresponding values in the circuit of Figure 3 are
It is 0.31mA and 206ps. Output stage gate like this
By supplementarily supplying power to Q ₃ and Q ₄ using the shunt resistor 132, both speed and output amplitude can be improved. The circuit in Figure 11a is a Doube-
The SGA operated by receiving the Rail signal input, but by changing the connection of the Q ₂ 135 part (indicated by A in the figure) and making it as shown in Figure 11 b, c, or d, It is possible to configure an SGA that operates with Single-Rail input as shown in FIG.
If input 13 is set as described above and the voltage applied to 130 is raised, Q ₂ will switch immediately after Q ₁ and Q ₃ switch, but Q ₄
Since the disable mechanism for
Sufficient operational margin is guaranteed. The SGAs shown in Figures 12 to 17, which will be described later, are also Single-
Although it also works as Rail input, the explanation regarding Single-Rail input will be omitted. Also, the speed of SGA is
As in this example, the power supply voltage is set to rise time 100ps.
We shall consistently discuss the time it takes for the output to reach a steady value when increasing from 0 mV to 11.2 mV. Note that this time will hereinafter be referred to as the SGA switching time. Embodiment 2: FIG. 12 shows a wiring diagram of an SGA which is another embodiment of the present invention. In the figure, 14
0 is the power supply bus, 141 is the 20Ω shunt resistor,
142 is a 3Ω load resistance, Q ₁ 143, Q ₂ 144,
Q ₃ 145, Q ₄ 146, Q ₅ 147, Q ₆ 148 are JI
It is. The output current of this circuit is 0.43mA, and the switching time is 241ps. In this way, the output of the output stage gate is connected to the JI, which operates as a buffer amplifier.
By doubling the control line of
After all, it is possible to secure the output amplitude while maintaining a fairly fast switching time. Embodiment 3: FIG. 13a shows a wiring diagram of an SGA which is another embodiment of the present invention. In this case, the JI used as the buffer amplifier in FIG. 12 is replaced with a Josephson Atto Weber Switch (hereinafter referred to as JAWS) type gate. this
For JAWS type gates, TA Fulton, SS
Pei and LNDunkleberger, “A simple high
performance current switched Josephson
logic”, Appl.Phys.Lett., vol.34, No.10, pp709
~711, May 15, 1979 (Reference 7). In the figure, 150 is a power supply bus, and 1
51 is a 20Ω shunt resistance, 152 is a 15Ω shunt resistance, 153 is a 3Ω load resistance, and 154 is a 3Ω load resistance. Q ₁ 155, Q ₂ 156, Q ₃ 157,
Q ₄ 158 is JI. Q ₅ 159, Q ₆ 160 are
This is the JAWS gate. FIG. 12b shows the configuration of the JAWS gate. In the same figure, 163 is 0.5Ω
161 and 162 are two and four Josephson junctions 33, respectively. The output current of this circuit is 0.53mA, and the switching time is 228ps. Example 4: In the circuit shown in Fig. 13, injection type logic gates called JAWS gates with input/output separation are used as Q ₅ and Q ₆ , but direct coupled logic gates of the same type are used.
There is a gate called Logic (hereinafter referred to as DCL).
This is T.Gheewale and A.Mukkeergee,
“Josephson direct coupled logic (DCL)”, in
IEDM Tech.Dig., pp482−484 (Washington
DC, Dec. 3-5, 1979) (Reference 8). An embodiment using this DCL gate is shown in FIG. 14a. This is shown in Figure 13a.
Q ₅ and Q ₆ are shown in Figure 14b.
It was replaced with DCL. In Fig. 14a, 170 is a power supply bus, 171 is a 20Ω shunt resistor, 172 is a 15Ω shunt resistor, 173 is a 3Ω load resistor, Q ₁ 175, Q ₂ 176, Q ₃ 177,
Q ₄ 178 is JI. Q ₅ 179, Q ₆ 180 are
It is a DCL gate. Also, in Figure 14b,
181 and 182 are two and four Josephson junctions 33, respectively. 183
is a resistance of 0.1Ω, and 184 is a resistance of 0.2Ω. The output current of this circuit is 0.54mA, and the switching time is 205ps. As described above, both the circuits shown in FIGS. 13 and 14 can generate an output current exceeding that of the circuit shown in FIG. 3. Note that the gates Q ₅ and Q ₆ in FIG. 13 may be replaced with a quantum interferometer such as a two-junction JI, that is, the portion b in FIG. 13 may be replaced as shown in FIG. 15. In addition, in Fig. 15, 19
1,192 is a Josephson junction, and 193 is an inductance. Embodiment 5: In the embodiments shown in FIGS. 13 to 15 above, SGAs using injection logic gates with input/output separation as buffer gates have _{been described} . ) replaced with such an injection type logic gate also shows good characteristics. Figure 16a shows an SGA using a JAWS gate as an output stage gate. In the figure, 200 is a power supply bus, 201 is a 20Ω shunt resistor, 202 is a 12Ω shunt resistor, 203 is a 3Ω load resistor, and Q ₁
205, Q ₂ 206 is JI, Q ₃ 207, Q ₄ 2
08 is JAWS gate. The structure of the JAWS gate is shown in FIG. 16b. In the same figure, 21
1,212 has 2.5 Josephson junctions 33, 2
13 is a joint in which eight pieces are lined up. 214 and 215 are resistances of 0.5Ω each. The output current of this SGA is 0.56mA, and the switching time is 140ps. Embodiment 6: FIG. 17a shows an SGA using a DCL gate as an output stage gate. In the figure, 220 is a power bus, 221 is a 20Ω shunt resistor, 222 is a 16Ω shunt resistor, 223 is a 3Ω load resistor, and Q ₁
225, Q ₂ 226 is JI. Q ₃ 227, Q ₄ 2
28 is a DCL gate, the structure of which is shown in FIG. 17b. In the figure, 231 and 232 are junctions in which two and six Josephson junctions 33 are lined up, respectively. The output current of this SGA is 0.72mA, and the switching time is 142ps. As mentioned above, by using an injection logic gate with input/output separation for the output stage gate, it is possible to ensure a large output current amplitude and a very fast switching time. Moreover, it goes without saying that a two-junction JI as shown in FIG. 15 may be used for the output stage gate. Table 1 summarizes the results described above regarding the output current and switching time of the SGA of FIG. 3 and the SGA of FIGS. 11 to 17.

〔Effect of the invention〕

As explained above, according to the present invention, a high output current amplitude is achieved while ensuring a stable operating margin.
An SGA circuit is obtained.

[Brief explanation of drawings]

Figure 1 is an explanatory diagram showing the basic configuration of SGA, Figure 2
Figure 3 is an explanatory diagram showing the basic configuration of an AND gate used in SGA, Figure 3 is an explanatory diagram showing the circuit configuration of SGA, Figure 4 is an explanatory diagram showing two types of SGA for reading data from a storage loop, Fifth,
Figures 6 and 7 are explanatory diagrams showing the circuit configuration of an SGA that inputs single data, Figure 8 is an explanatory diagram showing the configuration of an SGA using CIL for the output stage gate according to the conventional technology, and Figures 9 and 10 are 2 CILs and 4 JIs by conventional technology
FIG. Figures 11 to 17 are explanatory diagrams regarding the SGA according to the present invention.
Figure 2 shows an SGA in which the output stage JI gate output is passed through the JI control line twice, which operates as a buffer amplifier. Figure 13 shows a system in which the output stage JI gate output is used as an input to JAWS, which operates as a buffer amplifier. Figure 14 shows an SGA that uses the JI gate output of the output stage as an input to the DCL that operates as a buffer amplifier, and Figure 15 shows a two-junction SGA used for the buffer gate of the SGA.
JI, FIG. 16 shows an SGA using a JAWS gate as an output stage gate, and FIG. 17 shows an SGA using a DCL gate as an output stage gate. 33, 34, 74, 75, 76, 85, 94,
95, 161, 162, 181, 182, 19
1,192,211, 212,213,231,
232... Josephson junction, 44, 45, 46,
47, 64, 65, 66, 67, 73, 83, 1
03,104,114,115,118,11
9,124,125,126,127,134,
135, 136, 137, 143, 144, 14
5,146,147,148,155,156,
157, 158, 176, 177, 178, 20
5,206,207,208,225,226,
227, 228... Josephson magnetic quantum interferometer (JI), 84, 105, 106, 116, 117,
128, 129...CIL gate, 159, 160,
207,208...JAWS gate, 179,18
0,227,228...DCI gate.

Claims (1)

[Claims] 1. A flip-flop consisting of a detection stage gate that reads data from a master flip-flop, and an output stage gate that receives the output of the detection stage gate and generates a drive output to the logic circuit network at the next stage and thereafter. constitutes,
A master flip-flop and a slave flip-flop of an AC power-driven Josephson logic circuit, characterized in that the output stage gate is a flux-coupled Josephson magnetic quantum interferometer to which power is supplied independently from the detection stage gate. A self-gate AND circuit of a latch circuit consisting of. 2. In claim 1, the output stage gate is a self-contained magnetic quantum interferometer with an auxiliary gate current applied thereto.
Gate and circuit. 3. In claim 1, the output stage gate body is a first Josephson magnetic quantum interferometer, the subsequent stage is directly powered from a power supply line,
A self-gate AND circuit characterized in that it is a second Josephson magnetic quantum interferometer in which the output current of the output stage gate passes through two or more control lines in series. 4 Constructing a flip-flop consisting of a detection stage gate that reads data from a master flip-flop, and an output stage gate that receives the output of the detection stage gate and generates a drive output to the logic circuit network at the next stage,
An AC power-driven Josephson logic circuit, characterized in that the output stage gate is an injection type logic gate in which at least two Josephson junctions are connected through a resistance or inductance, and includes a Josephson element between an input signal terminal and an output signal terminal. A self-gate AND circuit of a latch circuit consisting of a master flip-flop and a slave flip-flop. 5. In claim 4, the output stage gate body is a Josephson magnetic quantum interferometer,
The subsequent stage is a Josephson Atto Weber switch type logic gate, a direct coupled logic type logic gate, and an injection type logic circuit that is powered directly from the power supply line and receives the output current of the output stage gate as input. Features a self-gate AND circuit.