JPH02138765A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH02138765A
JPH02138765A JP63189213A JP18921388A JPH02138765A JP H02138765 A JPH02138765 A JP H02138765A JP 63189213 A JP63189213 A JP 63189213A JP 18921388 A JP18921388 A JP 18921388A JP H02138765 A JPH02138765 A JP H02138765A
Authority
JP
Japan
Prior art keywords
lead frame
die pad
semiconductor device
chip
concentration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63189213A
Other languages
Japanese (ja)
Inventor
Jiyuri Katou
加藤　樹里
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP63189213A priority Critical patent/JPH02138765A/en
Publication of JPH02138765A publication Critical patent/JPH02138765A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To prevent the occurrence of passivation cracks by a method wherein the ends of a lead frame, a die pad, or a chip are rounded. CONSTITUTION:An LSI chip 3 is formed on a die pad 2 and a pad 5 is connected with a lead frame 6 by a gold wire 4, which is packaged with a molding resin 1. An end 10 of the lead frame, ends 11 and 11' of the die pad 2, or ends 12 of the chip 3 are rounded. By this setup, the concentration of a stress can be moderated. Therefore, the concentration of a thermal stress can be prevented when a device is sealed up with a molding resin, so that a semiconductor device with no passivation cracks can be obtained.

Description

【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、半導体装置に関する。特に熱ストレスに強い
高信頼度を必要とする半導体装置において有効である。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device. This is particularly effective in semiconductor devices that require high reliability and resistance to thermal stress.

［従来の技術］ 従来、モールド樹脂でパッケージされた集積回路におい
て、リードフレーム、ダイパッド、マタ［課題を解決す
るための手段］ 本発明では、リードフレーム、ダイパッド、マたは、チ
ップの少なくとも一部分の端をラウンド化するか、かど
を取ることにより、封止樹脂からの熱応力集中を回避し
ている。熱応力の集中が回避されるため、実装時や半導
体使用時にパッシベーションクラックが発生しない。[Prior Art] Conventionally, in an integrated circuit packaged with a molded resin, a lead frame, a die pad, and a matrix [Means for Solving the Problem] In the present invention, a lead frame, a die pad, a matrix, or at least a portion of a chip By rounding the edges or taking corners, concentration of thermal stress from the sealing resin is avoided. Since concentration of thermal stress is avoided, passivation cracks do not occur during mounting or semiconductor use.

［実施例］ 以下、実施例を用いて説明する。第１図は、本発明によ
るＬＳＩチップを樹脂封止した半導体装置の断面図であ
る。ダイパッド２上には、ＬＳＩチップ３が形成され、
パッド５とリードフレーム６は、金ワイヤ−４で接続さ
れ、モールド樹脂１によりパッケージされている。リー
ドフレーム６の端１０．ダイパッドの端１１．１１’　
　またはチップ３の端１２は、ラウンド化されている。[Example] Hereinafter, explanation will be given using an example. FIG. 1 is a sectional view of a semiconductor device in which an LSI chip according to the present invention is sealed with resin. An LSI chip 3 is formed on the die pad 2.
Pad 5 and lead frame 6 are connected by gold wire 4 and packaged with mold resin 1. End 10 of lead frame 6. Die pad end 11.11'
Alternatively, the end 12 of the chip 3 is rounded.

従来、これらの端は、はぼ垂直に構成されていたため、
樹脂の熱応力が生じ、パッジページ１ンクランクが多発
していた部分である。Traditionally, these edges were configured almost vertically;
This is the area where thermal stress of the resin occurred and many page 1 cranks occurred.

［発明の効果コ 本発明では、この部分を第２図に示すようにラウンド化
するか、第６図に示すようにかどを取ることにより、ス
トレスの集中を緩和した。従って、本発明ではモールド
樹脂封止時、実装時、及び半導体装置使用時の熱応力集
中がなくパッシベーションクラックの発生しない高信頼
度の半導体装置を提供する。[Effects of the Invention] In the present invention, stress concentration is alleviated by rounding this part as shown in FIG. 2 or by cutting corners as shown in FIG. Therefore, the present invention provides a highly reliable semiconductor device in which there is no thermal stress concentration during mold resin sealing, mounting, and use of the semiconductor device, and no passivation cracks occur.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明によるＬＳＩを樹脂封止した半導体装置
の断面図。 第２図は本発明によるダイパッド端の構造断面図。 第６図は本発明によるリードフレーム端のもη膜断面図
。 １・・・・・・・・・モールド樹脂 ２・・・・・・・・・ダイパッド ３・・・・・・・・・ＬＳＩチップ ４・・・・・・・・・金ワイヤ ５・・・・・・・・・パッド ６・・・・・・・・・リードフレーム １０・・・・・・リードフレーム端 １１．１１’　・・・・・・ダイパッド端１２・・・・
・・チ、プ端FIG. 1 is a sectional view of a semiconductor device in which an LSI according to the present invention is sealed with resin. FIG. 2 is a structural cross-sectional view of the die pad end according to the present invention. FIG. 6 is a sectional view of the η film at the end of the lead frame according to the present invention. 1...Mold resin 2...Die pad 3...LSI chip 4...Gold wire 5... ......Pad 6...Lead frame 10...Lead frame end 11.11'...Die pad end 12...
...chi, pu end

Claims (1)

【特許請求の範囲】[Claims] モールド樹脂によりパッケージされた集積回路において
、リードフレーム、ダイパッド、またはチップの端がラ
ウンド化されていることを特徴とする半導体装置。1. A semiconductor device characterized in that, in an integrated circuit packaged with a mold resin, the ends of a lead frame, a die pad, or a chip are rounded.
JP63189213A 1988-07-28 1988-07-28 Semiconductor device Pending JPH02138765A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63189213A JPH02138765A (en) 1988-07-28 1988-07-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63189213A JPH02138765A (en) 1988-07-28 1988-07-28 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH02138765A true JPH02138765A (en) 1990-05-28

Family

ID=16237443

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63189213A Pending JPH02138765A (en) 1988-07-28 1988-07-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH02138765A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992004730A1 (en) * 1990-09-10 1992-03-19 Fujitsu Limited Semiconductor device and its manufacturing process

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992004730A1 (en) * 1990-09-10 1992-03-19 Fujitsu Limited Semiconductor device and its manufacturing process
US5440170A (en) * 1990-09-10 1995-08-08 Fujitsu Limited Semiconductor device having a die pad with rounded edges and its manufacturing method

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