JPH02140860U

JPH02140860U -

Info

Publication number: JPH02140860U
Application number: JP4828089U
Authority: JP
Priority date: 1989-04-26
Filing date: 1989-04-26
Publication date: 1990-11-26

Description

[Brief explanation of drawings]

第１図ａ，ｂ，ｃ，ｄはいずれも本考案の一実
施例を示すもので、第１図ａは制御基板への実装
例を示す図、第１図ｂはＩＣパツケージにコンデ
ンサを実装した状態を示す斜視図、第１図ｃは第
１図ｂのＣ−Ｃに沿う矢視断面図、第１図ｄはＩ
Ｃパツケージとコンデンサとの接続図、第２図ａ
，ｂはいずれも従来例を示すもので、第２図ａは
第１図ａ相当図、第２図ｂは第１図ｂ相当図、第
３図ａ，ｂはいずれも従来例の他の例を示すもの
で、第３図ａは第１図ａ相当図、第３図ｂは第１
図ｂ相当図、第４図は従来のＩＣパツケージとコ
ンデンサとの接続態様を示す第１図ｄ相当図であ
る。図において、１……デユアルインラインパツケ
ージ集積回路（ＩＣパツケージ）、５……チツプ
コンデンサ（コンデンサ）、７……ＩＣチツプ、
８ａ，８ｂ……端子、９……電源供給用リード、
１０……アース用リードである。 Figures 1a, b, c, and d all show an embodiment of the present invention. Figure 1a shows an example of mounting on a control board, and Figure 1b shows a capacitor mounted on an IC package. FIG. 1c is a sectional view taken along line C-C in FIG. 1b, and FIG. 1d is a perspective view showing the I
Connection diagram of C package and capacitor, Figure 2a
, b show conventional examples; FIG. 2 a is a diagram equivalent to FIG. 1 a, FIG. 2 b is a diagram equivalent to FIG. 1 b, and FIGS. Figure 3a is a diagram equivalent to Figure 1a, and Figure 3b is a diagram corresponding to Figure 1.
FIG. 4 is a diagram corresponding to FIG. 1B, and FIG. 4 is a diagram corresponding to FIG. In the figure, 1... dual in-line package integrated circuit (IC package), 5... chip capacitor (capacitor), 7... IC chip,
8a, 8b... terminal, 9... power supply lead,
10...This is a grounding lead.

Claims

[Scope of utility model registration request]

A pair of terminals for mounting a capacitor on the package are provided on the outside of the IC package that houses the IC chip, and these terminals are connected to the IC.
An IC package with a capacitor mounting function, which is connected to a power supply lead and a ground lead inside the package.