JPH02141011A - Agc circuit - Google Patents

Abstract

PURPOSE:To eliminate operations of a transistor in an undesired operating area and influences of the operations to other circuits by providing a transistor circuit driven by the output of a comparator and connecting a reduction controlling means to the output side of the transistor circuit. CONSTITUTION:The AGC circuit is constituted by providing a transistor circuit 6 driven by the output of a comparator 4 between the output end of the comparator 4 and a control current supplying means Q6 and connecting a reduction controlling means Q7 to the output side of the circuit 6. Accordingly, when a gain controlling current is reduced to the smallest level by dropping the output of the circuit 6, the voltage on the input side of the transistor Q8 of the circuit 6 is not reduced forcibly. Therefore, the gain controlling current can be reduced to a prescribed value while the comparator 4 for forming ACC error voltage is normally operated without giving any influence on the comparator 4.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an AGC circuit, and more particularly to muting an AGC circuit.

With the development of the use of external input in television receivers, VTRs, etc., it is required that the television signal be blocked in the IF circuit when external input is used.

However, since signal leakage also occurs at the switch that switches between external input and TV input, it is necessary to mute the IF circuit itself. In this case, -a is muted at the output stage of the IF circuit, but in order to improve the muting characteristics, it is effective to further minimize the gain of the variable gain amplifier in the preceding stage.

FIG. 2 is an example of this type of AGC circuit that has been used conventionally. The variable gain amplifier (
A part of the video signal amplified in step 2) is detected by a detector (3) and compared with a reference voltage by a comparator (4). AGC error detection is performed by this comparison. Note that the output voltage of the wave detector (3) is high when the output signal of the variable gain amplifier (2) is small, and becomes low when the output signal is large. Comparator (4) is a differential pair transistor (Qt
) (Qt), constant current source transistor (C3), resistor (R+), current mirror connected transistor (+
14) (Qs), a reference voltage (Vref) is applied to the base of the first differential pair transistor (Q,), and a detector (Vref) is applied to the base of the second differential pair transistor (Qz). 3) is applied. The output of this comparator (4) is received by a capacitor (CI) to form an AGC error voltage (V), and this AGC error voltage (vl) determines the emitter voltage (v2) of the transistor (Q, ).

The magnitude of the gain control current (++) that determines the gain of the variable gain amplifier (2) is proportional to the emitter voltage (ν2).

The AGC circuit operates in the loop described above, but in order to minimize the gain of the variable gain amplifier (2), a switch (
5) is provided, and by turning on this switch (5) with a mute signal, the base voltage of the transistor (Q,) (therefore, the AGC error voltage V,) is forcibly lowered.

, B tries to turn on. However, when the above voltage (vl) is forcibly lowered, the first differential pair transistor (0,) and the constant current source transistor (C3) go out of their normal operating range, Reference voltage (Vr
If the impedance of the supply circuit of ef) is low, an inconvenience occurs in that an excessive current flows from the base to the collector of the first differential pair transistor (0,).

Also, due to saturation of the transistor (0,), its base voltage (V:l) decreases, so if a transistor constituting a constant current source of another circuit is connected to this base,
It will have a negative impact on it.

The present invention has been made in view of the above points, and includes A.
AGC that can lower the gain control current to a predetermined value while keeping the GC error voltage forming comparator operating normally.
The purpose is to provide circuits.

In order to achieve the above object, the present invention includes a comparator for AGC error detection configured with a differential amplifier, and a gain generated based on the output of the comparator. gain control current supply means for supplying a control current to the variable gain amplifier; and a gain control current supply means for supplying a control current to the variable gain amplifier;
a reduction control means for reducing the 4'J■ current to a predetermined value;
In the AGC circuit, a transistor circuit driven by the output of the comparator is provided between the output end of the comparator and the control current supply means, and the reduction control means is connected to the output side of the transistor circuit. There is.

According to this configuration, when the gain control current is minimized by reducing the output of the transistor circuit, the voltage on the input side of the transistor is not forcibly reduced, so there is no effect on the comparator. do not have.

In this embodiment, the same parts as those in the conventional example shown in FIG. A transistor circuit (6) is connected, and a switching transistor (Q, ) for muting is connected to the output side of this transistor circuit (6).
are connected. The transistor U path (6) is connected between a transistor (gate) whose base receives the voltage (ν1) generated in the capacitor (C1) and the emitter of the transistor (08) and the ground point, although it is not necessary to be limited to this. It consists of a resistor (R3) connected to the collector side, a current mirror circuit (7) connected to the collector side, and a resistor (R2) connected between the output end of the current mirror circuit (7) and the ground point. has been done.

In addition, the current mirror circuit (7) is a transistor (mouth)
A PNPI-transistor (Ql.) whose collector and base are connected to the collector of the transistor (Ql.) and whose emitter is connected to the power supply voltage line (8) is the same (the base is connected to the said transistor (Ql.)
, ), the emitter is connected to the power supply voltage line (8), and the collector becomes the output terminal.
) transistors (Q, ).

A muting transistor (Q,
) has its collector connected to the output end (collector) of the PNP transistor (gate), and its emitter connected to the ground point. A mute signal is applied to the base.

The emitter voltage of the transistor (Q8) is (V3),
If the base voltage of the transistor (portion b) is (v4), the base voltage of the transistor (Q, ) is normally higher than (vl).
Emitter voltage (V,
) and the resistor (R1) cause a current (l, ) to flow. For simplicity, if we assume that the current flowing through each PNP transistor (Q9) (Ql.) is 1=1, then It=13, and the base voltage (V,) of the transistor (2) is (■2) and (
R2), and is determined by the following formula.

V4=hRz=hRz= ” R1= ” (VI V
IE) R, R3 From this, a voltage proportional to the AGC error voltage is applied to the transistor (Q6). Here, the gain control current (1
1) to a predetermined value (zero in this example), it is sufficient to lower the base voltage of the transistor (Q&), so a mute signal is applied to the base of the transistor (Q7) to turn on the transistor (07). .

At this time, if the collector current of the transistor (Q, ) is greater than the collector current of the transistor (Q, ), the base voltage (v4) decreases, and finally the transistor (Q, too) becomes cut-off.

However, even if the base voltage (v4) is lowered in this way, the voltage (ν1) on the input side of the transistor circuit (6)
does not fall, so comparator (4) operates normally.

As described above, according to the present invention, the gain control current can be lowered to a predetermined value while the comparator that forms the AGC error voltage is kept in normal operation, so that the transistor constituting the comparator can be prevented from undesired operation. It does not operate in this area and does not affect other circuits.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an AGC circuit embodying the present invention. FIG. 2 is a circuit diagram of a conventional example. (2) --- Variable gain amplifier. (4) - Comparator. (6) -) transistor circuit. (L) - gain control current. (vl)・-AGC error voltage. (06)...-Transistor (control current supply means). (Ol) - Mute transistor (reduction control means)
.

Claims (1)

[Claims] (1) A comparator for AGC error detection configured with a differential amplifier; gain control current supply means for supplying a gain control current generated based on the output of the comparator to a variable gain amplifier; and reduction control means for reducing the gain control current to a predetermined value in order to minimize the gain, the AGC circuit having an AGC circuit that is driven by the output of the comparator between the output terminal of the comparator and the control current supply means. 1. An AGC circuit comprising: a transistor circuit, the reduction control means being connected to the output side of the transistor circuit.