JPH02141014A - Waveform equalization circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a waveform equalization circuit provided in a signal generation circuit that generates a binary digital signal by detecting the peak position of an input analog signal.

[Prior Art] Conventionally, in a storage information reading circuit, a circuit demodulates the peak position of a reproduced analog signal read by a storage information detection means into a binary digital signal using a peak detector using differentiation. It has been known.

FIG. 4 is a block diagram showing a specific configuration of such a peak detector (demodulation circuit).

This peak detector includes a differentiator 10 that passes high-frequency components of an input signal, a low-pass filter 11 that reduces high-frequency noise components and improves the signal-to-noise ratio, and a zero-cross level of the input signal as a boundary. and a zero cross comparator 12 that performs comparison operation.

A level comparator 13 operates to compare the input signal using a certain potential level VTR as a boundary, and the input signal is
It has a delay circuit 14 that delays by 2, and a product logic circuit 15 that outputs the product of two input signal levels.

The differentiator 10 has a reproduced analog signal input section (■ in FIG. 4), into which a reproduced analog signal that has passed through a waveform equalization circuit, which will be described later, is input. Output of low-pass filter 11! g
From A (■ in FIG. 4), the reproduced analog signal is differentiated by a differentiator 10, and a signal from which high-frequency noise components are removed is generated by a low-pass filter 11. Here, the peak position of the reproduced analog signal corresponds to the zero-crossing point of the output signal from the low-pass filter 11. The zero-cross comparator output, which is inverted by the zero-cross comparator 12 as a boundary of this zero-cross point, is supplied to one input terminal of the product logic circuit (■ in FIG. 4).

Further, the output signal of the low-pass filter 11 is inverted by the level comparator 13 with a predetermined threshold level VTH as the boundary, and this level comparator output (
The signal (circled ■ in FIG. 4) is supplied to the delay circuit 14, delayed by time t2, and supplied to the other input terminal of the product logic circuit 15 (circle ■ in FIG. 4).

Then, the output signal of the product logic circuit is obtained as final digital demodulated data.

FIG. 5 is a waveform diagram showing the process of generating such final digital demodulated data. Note that ■ to ■ in the figure indicate signal waveforms at various parts of the peak detector in FIG. 4.

Further, as a waveform equalization circuit for supplying a waveform-equalized input analog signal to such a peak detector, the one shown in FIG. 6 is known.

This waveform equalization circuit includes delay circuits 1 and 2 that delay the input signal by a certain time t1, a variable circuit 7 that varies the signal level, an inversion circuit 8 that inverts the signal level, and a buffer 9. .

In this waveform equalization circuit, the input signal is output as a signal without delay at point A in FIG. 6, a signal delayed by tl at point B, and a signal delayed by 2tl at point 0. The signals at point A and point 0 are varied to a predetermined level by variable circuit 7 and inverted by inverting circuit 8 . Further, such an inverted signal and L are added to the signal at point B after passing through the buffer 9, and outputted as an output signal M whose waveform has been equalized.

FIG. 7 (1) is a waveform diagram showing the process when a single pulse waveform input signal is waveform equalized as described above,
FIG. 7(2) is a waveform diagram showing a process when two consecutive pulse waveform input signals are waveform-equalized.

Assuming that the signal to be waveform-equalized as described above has the waveform at point B in Figure 6, the portion of the input signal where the code amount interferes will be equalized as shown in Figure 7 (2). , level r
The amplitude range is expanded from NJ to level "0", and the code of the part where the code amount interferes can be easily distinguished, thereby preventing malfunction.

[Problem to be solved by the invention] However, in the conventional waveform equalization circuit as described above,
As the effect of waveform equalization is strengthened, the degree of code amount interference is reduced, but as a result, a part of torsional rebound (shelf width P in Fig. 7) occurs, so that In the peak detector having this configuration, there is a possibility that the following problems may occur.

In other words, when a waveform-equalized signal is input to the peak detector with the above configuration, this signal is differentiated, and in addition to the original signal portion, the rebound portion that is derived as a result of the waveform equalization is differentiated. Therefore, as shown in FIG. 8, a derived waveform portion H occurs in the output of the low-pass filter 11 based on the rebound portion Q, and
As shown in the figure, when the derived waveform portion R exceeds the threshold level VTR of the level comparator 13, as seen in the generated signals of the level comparator 13 and the delay circuit 14 (■ in FIG. 8), pseudo signal R
On the other hand, D is generated.

Since the output of the zero cross comparator 12 is unstable in the timing period of the pseudo signal RD of the output signal of the delay circuit 14, the pseudo data RID is demodulated in the digital demodulated data in addition to the original demodulated data, and henceforth There is a problem that affects the data demodulation operation.

In addition, Figures 9 (1) to (3) show the waveform equalization ratio when the original signal that is not passed through the waveform equalization circuit is demodulated with a peak detector and when it is passed through the waveform equalization circuit. FIG. 7 is a waveform diagram showing a comparative example of demodulated signals.

As can be seen from Figure 9 (1), conventionally, when demodulating digital data by peak detection, the waveform If an analog reproduced signal is demodulated as it is without correction such as equalization, data will be lost in the code amount interference region, making it impossible to demodulate correct data.

Therefore, as shown in Figure 9 (2), methods are used to demodulate data by reducing code amount interference using techniques such as waveform equalization, but as the interference reduction effect increases, the amount of interference Although the reduction effect increases.

On the other hand, the rebound caused by equalization also increases.

As a result of data demodulation, pseudo data RID is generated, and correct data demodulation cannot be performed.

On the other hand, even if waveform equalization is performed, as shown in FIG. 9 (3), if the interference reduction effect is weakened, the bounce caused by equalization will not be so large, and the above pseudo data RID will not occur. However, on the other hand, it becomes impossible to demodulate correct data in the original interference area.

As described above, according to the conventional method, it is necessary to reduce the code amount interference by waveform equalization and prevent the generation of pseudo data by data demodulation, and even if the code amount interference increases, the strong Waveform equalization could not be performed.

In addition, as a conventional waveform equalization means, a generally well-known transversal filter is used that uses a cosine filter whose transfer characteristic is H(ω) = 1-2XK coSωt (K: equalization rate coefficient, t: delay time). In waveform equalization using characteristics, the number of delay circuits in FIG. 6 is increased.

It is generally known that by performing waveform equalization using more delayed signals, the level P of bounce can be smoothed and suppressed to a low level even if the waveform equalization is strengthened. but,
This is just an ideal, but in reality it is not very practical considering the increase in the number of delay elements used and the cost. It has become difficult.

SUMMARY OF THE INVENTION An object of the present invention is to provide a waveform equalization circuit that does not cause bounce even when waveform equalization is strengthened, effectively prevents code amount interference, and can perform correct demodulation. .

[Means for Solving the Problems] The present invention provides a waveform equalization circuit provided in a signal generation circuit that generates a binary digital signal by detecting a peak position of an input analog signal, in which the input analog signal is processed for a predetermined period of time. a first delayed analog signal;
Furthermore, a delay means for generating a second delayed analog signal delayed by the same predetermined time; and inputting the input analog signal and the first and second delayed analog signals; Delayed analog signal, the first
For three combinations of the delayed analog signal and the second delayed analog signal, and the input analog signal and the second delayed analog signal, the amplitude levels of the two signals in each set are successively compared, and the lower one is a logic operation means that outputs an amplitude level of , and a logic operation means that outputs an amplitude level of the input analog signal based on the output signal of the logic operation means for the combination of the input analog signal and the second delayed analog signal as a reference, and based on this output signal and other combinations. a first analog calculating means for obtaining a difference signal from the output signal; a rectifying means for rectifying the output difference signal of the analog calculating means; and a variable means for changing the signal level of the rectifying means to output a waveform equalization correction signal. and second analog calculation means for synthesizing the waveform equalization correction signal and the second delayed analog signal.

[Operation] In the present invention, the waveform equalization correction signal obtained through each of the arithmetic means, the rectification means, and the variable means is temporally in phase with the first delayed analog signal. Therefore, by combining this waveform equalization correction signal and the first delayed analog signal to obtain a waveform equalization signal, even when the waveform equalization rate is increased, the waveform can be equalized without bouncing the tail portion of the signal. Even when this waveform equalized signal is demodulated, proper demodulation processing can be performed without generating pseudo data.

[Embodiment] Fig. 1 is a block diagram showing a waveform equalization circuit according to an embodiment of the present invention, and Fig. 2 (1) and (2) show the output waveforms of each part of this waveform equalization circuit. FIG.

This waveform equalization circuit consists of delay circuits 21 and 22 that delay an input analog signal by a delay time t1 with constant frequency characteristics.
, logical sum operation circuits 23 to 25 that successively compare two input signals and select and output the lower level signal at a certain point in time, a full-wave rectification and synthesis circuit 26, and an aftereffect rectification and synthesis circuit 26 Variable circuit 2 that changes the output signal level
7.

In the above configuration, the analog signal input from the input terminal (A in FIG. 1) of the first delay circuit 21 is transmitted to the output stage (B in FIG. 1) of the first delay circuit 21. It is output as a first delayed analog signal delayed by t1 in time with respect to the input analog signal, and at the output stage (C in FIG. 1) of the second delay circuit 22, the time delay with respect to the input analog signal is output. It is output as a second delayed analog signal delayed by 2tl.

The input analog signal and the second delayed analog signal are inputted to the first OR operation circuit 23, and their amplitude levels are successively compared, and as shown in F in FIG. The signal level of is selected and output.

Similarly, the input analog signal and the first delayed analog signal are input to the OR circuit 24, and the first delayed analog signal and the second delayed analog signal are input to the OR circuit 25. By inputting the signals and performing successive comparisons, as shown in Fig. 2 and E,
The lower signal level is selected and output.

Note that in FIG. 2, symbols a to e indicate the amplitude level of each signal.

Then, a subtracted output signal (G in FIG. 2) obtained by subtracting the output of the OR circuit 24 from the output of the OR circuit 23
and the output of the logical sum calculation circuit 23, the logical sum wave 'X circuit 25
The subtracted output signal (H in Figure 2) obtained by subtracting the output of is
The signal is input to the full-wave rectification/synthesis circuit 26 and rectified, and the output composite signal is obtained as a waveform equalization correction signal as shown at I in FIG.

This waveform equalization signal processing further includes a variable circuit 27.
After the waveform equalization level is arbitrarily adjusted, the signal is added to the first delayed analog signal as shown in FIG. 3 (1) and (2), and is indicated by J in FIG. is generated as the final waveform equalized signal.

The waveform equalization correction signal and the first delayed analog signal are in phase with each other in time, so the waveform equalization rate of the waveform equalization signal is changed by varying the amplitude level of the waveform equalization correction signal. Even if you strengthen it.

Unlike the conventional method, there is no rebound in the tail portion of this waveform equalized signal, and even when this waveform equalized signal is processed by the decoding circuit using the peak detection method shown in Fig. 4, the rebound portion does not occur. Pseudo data is no longer demodulated, and good demodulation processing can be performed.

Further, if the delay element used in the delay circuit is one with a tap output, only one delay element is required, which reduces costs and requires less mounting area, which is advantageous in circuit production.

[Effect 1 of the Invention According to the present invention, a waveform equalization correction signal and a first delayed analog signal whose temporal phases match each other are generated, and these are synthesized to obtain a waveform equalization signal. Even when the level of the equalization correction signal is raised to strengthen the waveform equalization rate, it is possible to generate a waveform equalized signal without a bounce portion unlike the conventional one.

Therefore, even when this waveform-equalized signal is demodulated, it is possible to perform appropriate demodulation processing without generating pseudo data and effectively preventing code amount interference.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a waveform equalization circuit according to an embodiment of the present invention. FIGS. 2(1) and (2) are waveform diagrams showing output waveforms in each part of the waveform equalization circuit of the same embodiment, and FIG.
1) shows the case where a single pulse waveform input signal is waveform-equalized, and FIG. 2 (2) shows the case where two consecutive pulse waveform input signals are waveform-equalized. FIGS. 3(1) and (2) are waveform diagrams showing the output waveform of the final waveform equalized signal of the waveform equalization circuit of the same embodiment, and FIG. The case of a pulse waveform input signal is shown, and FIG. 3 (2) shows the case of two consecutive pulse waveform input signals. FIG. 4 is a block diagram showing a specific configuration of a peak detector provided with a waveform equalization circuit. FIG. 5 is a waveform diagram illustrating the demodulation operation in the peak detector. FIG. 6 is a block diagram showing an example of a conventional waveform equalization circuit. 7(1) and (2) are waveform diagrams for explaining the waveform equalization operation of the waveform equalization circuit shown in FIG.
) shows the case where a single pulse waveform input signal is waveform-equalized, and FIG. 7(2) shows the case where a single pulse waveform input signal is waveform-equalized. A case is shown in which two consecutive pulse waveform input signals are waveform-equalized. FIG. 8 is a waveform diagram showing output waveforms at each part of the peak detector. FIG. 9(1) is a waveform diagram showing an example of an output waveform when the peak detector demodulates the original signal that is not passed through the waveform equalization circuit. FIG. 9(2) is a waveform diagram showing an example of an output waveform when a waveform equalized signal with a high waveform equalization rate is demodulated by a peak detector. FIG. 9(3) is a waveform diagram showing an example of an output waveform when a waveform equalized signal with a low waveform equalization rate is demodulated by a peak detector. l, 22...Delay circuit, 3.24.25...OR operation circuit, 6...Aftermath rectification and synthesis circuit, 7...Variable circuit.

Claims (1)

[Claims] By detecting the peak position of the input analog signal,
In a waveform equalization circuit provided in a signal generation circuit that generates a binary digital signal, a first delayed analog signal is obtained by delaying the input analog signal by a predetermined time, and a second delayed analog signal is further delayed by the same predetermined time.
a delay means for generating a delayed analog signal; a delay means for receiving the input analog signal and first and second delayed analog signals; For three combinations of the signal and the second delayed analog signal, and the input analog signal and the second delayed analog signal,
logical operation means for successively comparing the amplitude levels of the two signals in each set and outputting the lower amplitude level; a first analog calculation means that uses this output signal as a reference and obtains a difference signal from an output signal of a logical calculation means based on another combination; a rectification means that rectifies the output difference signal of the analog calculation means; this rectification means a variable means for outputting a waveform equalization correction signal by changing the signal level of the waveform equalization correction signal; and a second analog calculation means for synthesizing the waveform equalization correction signal and the first delayed analog signal. Features a waveform equalization circuit.