JPH02141860A - Data transfer controller - Google Patents

Abstract

PURPOSE:To execute a data transfer to a partial write impossible interface from a partial write possible interface by sending out data to the partial write impossible interface, when write of all the data which are sent is ended. CONSTITUTION:A data transfer controller 1 transfers the upper 1 byte of an interface 2 and the lower 1 byte to a local memory 6 and a memory 5, respectively. When write of all data to the local memory 5 and 6 is ended, subsequently, data is sent out of a partial write impossible interface driver 11. Next, in order of writing it in the local memory 5 and 6, the upper byte of the local memory 6 and the lower byte of the local memory 5 are sent out to the upper side of a partial write impossible interface 3 and the lower side of the partial write impossible interface 3, respectively from the partial write impossible interface driver 11 and the transfer is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention is applied to an information processing device. The present invention relates to a data transfer control device that controls data transfer.

〔overview〕

In a data transfer interface that transfers data from a partially writable interface to a non-partially writable interface, the present invention transfers data as is when all of the sent data is valid, and changes the byte position when some of the data is valid. By calculating address values based on mask information, specifying local memory, and writing and outputting data, data can be transferred with a small hardware configuration and simple control. be.

[Conventional technology]

When transferring data from a partially writable interface to a non-partially writable interface, the data transferred from the middle of a word on the partially writable interface is transferred from the beginning of the word on the partially writable interface. There must be. For example, when the partially writable interface is 2 bytes, more effective data is transferred from the lower byte of the first word.

At this time, assuming that the interface that cannot be partially written is also 2 bytes, when sending data to this interface, it is necessary to send data that is more effective from the upper part of the first word.

Conventionally, after storing two words of data to be received in two registers for data transfer in a data transfer device,
The lower 1 byte of the first data transfer register is transferred to the upper 1 byte of the local memory, the upper 1 byte of the second data transfer register is transferred to the lower 1 byte of the local memory, and then stored. 1 word of data is stored in the first data transfer register, and then the lower 1 byte of the second data transfer register is transferred to the upper 1 byte of the local memory. 1
The byte was transferred and stored in the lower 1 byte of local memory. Thereafter, the data is stored in the local memory by alternately using the 2-word first and second data transfer registers and similarly transferred, and the data is transferred directly by sending this data to an interface that cannot partially write. was going on.

[Problem that the invention seeks to solve]

In the conventional data transfer device described above, when data is transferred from a partially writable interface to a non-partially writable interface, the former interface has registers for two words, and data from the system memory is transferred to those registers. Since data is transferred by receiving signals alternately, the hardware becomes large and the control becomes complicated.

The present invention aims to eliminate such drawbacks, and provides a device that can transfer data from a partially writable interface to a non-partially writable interface with a small circuit configuration and simple control. shall be.

[Means for solving problems]

The present invention provides a local memory unit that is connected to a first partially writable interface that is a transfer source and a second interface that is not partially writable that is a transfer destination, and that temporarily stores data transferred from the first interface. and address means for generating an address for the local memory section,
A mask storage unit is provided for storing a mask state input to the first interface, and the local memory unit has memories of the same capacity arranged in parallel, and the local memory unit stores the mask state inputted to the first interface. It is characterized in that it includes a data handling section that distributes an interface to memories arranged in parallel, and that the addressing means includes means for calculating an address to be given to the memory section according to the contents of a mask storage section.

[Effect]

When valid data from the upper byte of the first word of the partial writeable interface to both the upper and lower bytes and mask information indicating the same are sent, the mask storage section stores the mask information, and the address calculation section stores the mask information. The data is temporarily written in the local memory section by sending the address as is, and when all data writing is completed, the data is sent to the partially write-enabled interface.

When data in which only the lower byte is valid and mask information indicating this is sent from the lower byte of the first word of the partially write-enabled interface, the mask storage unit stores the mask information, and the data handling unit stores the upper byte and the data. Invert the lower byte. At this time, the address calculation section calculates and sends out the data in the address section, temporarily writes the sent data to the local memory section determined by the calculation, and when all data has been written, the partial write impossible interface Send data to.

Thereby, data can be transferred from a partially writable interface to a partially writable interface with a small circuit configuration and simple control.

〔Example〕

Next, embodiments of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

The embodiment of the present invention includes a local memory section 5 which is connected to a partially writable interface 2 as a transfer source and a partially writable non-writable interface 3 as a transfer destination, and temporarily stores data transferred from the partially writable interface 2. .6 and this local memory section 5
．． The present invention is further provided with an address unit 7 and an address calculation unit 8 that constitute address means for generating the addresses of No. 6, and further includes a mask storage unit that stores the mask state manually input to the partially writable interface 2, which is a feature of the present invention. 12 is provided, and a local memory section 5.6 has memories of the same capacity arranged in parallel.
6 is equipped with a data handling unit 4 that distributes the partially writable interface to memories arranged in parallel according to the contents of the mask storage unit 12, and the address unit 7 and the address calculation unit 8 constituting the address means are connected to the mask storage R12. local memory section 5 according to the contents of
．． It includes means for calculating the address given to 6.

The local memory section 5.6 is connected to a partially writable interface driver 11, and a partially writable interface 3 is connected to this partially writable interface driver.

The operation of the embodiment of the present invention configured as described above will be explained.

First, consider a case where data transfer is performed from the upper byte of the first word of the partially writable interface 2. In this case, if two or more bytes of data are transferred, both the upper and lower bytes of the first word are valid data, so mask information indicating this is sent along with the data.

The data transfer control device 1 stores the mask information of the first word in the mask storage section 12, and since both bytes are valid, the data transfer control device 1 directly transfers the mask information to the partially writeable interface 2.
The upper one byte of is transferred to the local memory unit 6, and the lower one byte is transferred to the local memory unit 5. At this time, since both bytes of data in the partially writable interface 2 are valid, the address calculation section 8 uses the address section 7.
The data is sent as is to the lower address line 9 of the local memory. Here, write pulses are output to the local memories 5 and 6 to perform writing, and the address section 7 is incremented by 2 bytes.

Subsequently, when the next word is sent, mask storage unit 1
2, it is remembered that both bytes of the first word are valid, so the data is written to the local memories 5 and 6 using the same procedure as above. Thereafter, data is written to local memories 5 and 6 in the same manner up to the last byte.

When writing of all data to the local memories 5 and 6 is completed, data is then sent from the partially writable interface driver 11 to the partially writable interface 3.

This means that in the order of writing to local memories 5 and 6, the upper byte of local memory 6 is partially written to the upper side of interface 3, and the lower byte of local memory 5 is partially written to the lower side of interface 3, which is not partially writeable. The data is sent from the interface driver 11 to complete the transfer. This state is shown in FIG.

Next, consider a case where data transfer is performed from the lower byte of the first word of the partially writable interface 2. In this case, since only the lower byte of the first word is valid data, mask information indicating this is sent along with the data. Then, the data transfer control device 1 stores the mask information of the first word in the mask storage section 12, and since only the lower one byte is valid, the data handling section 4 inverts the upper byte and the lower byte and stores the mask information in the partially writeable interface 2. The upper byte of is transferred to the local memory section 5 and the lower byte of is transferred to the local memory section 6. Also, at this time, since only the lower byte of the data in the partially writable interface 2 is valid, the address calculation section 8 subtracts one byte from the data in the address section 7 and sends it to the local memory lower address line 9. here,
Write pulses are issued to the local memories 5 and 6 to perform writing, and the address section 7 is incremented by 2 bytes.

Subsequently, when the next word is sent, mask storage unit 1
2, it is remembered that only the lower 1 byte of the first word is valid, so it is written to the local memory using the same procedure as above. Thereafter, data is similarly written to local memories 5 and 6 up to the final byte. When all the data has been written to the local memories 5 and 6, the data is sent to the partially writable interface 3. This means that in the order of writing to the local memories 5 and 6, the upper byte of the local memory is transferred to the upper side of the interface, and the lower byte of the local memory is transferred to the lower side of the partially write disabled interface 3.
The transfer is completed by sending it from. This state is shown in FIG.

〔Effect of the invention〕

As described above, according to the present invention, data can be transferred from a partially writable interface to a partially writable interface with a small circuit configuration and simple control.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a diagram showing an example of data transfer in the case where both bytes of the first word are valid data according to the embodiment of the present invention. FIG. 3 is a diagram showing an example of data transfer when only the lower 1 byte of the first word is valid data according to the embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Data transfer control device, 2... Partially writable interface, 3... Partially writable interface, 4... Data handling unit, 5
... Local memory (lower 1 byte), 6... Local memory (upper 1 byte), 7... Address section, 8... Address calculation section, 9... Local memory lower side address line, 10 . . . Local memory upper address line, 11 . . . Partially writable interface driver, 12 . . . Mask storage section.

Claims (1)

[Claims] 1. Connected to a first interface that is a transfer source that is partially writable and a second interface that is a transfer destination that is not partially writable, and that temporarily stores data transferred from the first interface. A data transfer control device comprising: a local memory unit that stores a mask state; and an address unit that generates an address for the local memory unit; Memories of equal capacity are arranged in parallel, and the local memory section includes a data handling section that distributes the first interface to the memories arranged in parallel according to the contents of the mask storage section, and the addressing means includes: A data transfer control device comprising means for calculating an address to be given to the memory section according to the contents of a mask storage section.