JPH02141971A - Clock regenerating circuit - Google Patents

Abstract

PURPOSE:To suppress the deviation of a system clock by providing a lock monitoring circuit, monitoring the lock operation state of a PLL, switching the PLL to a selector when abnormality occurs in the state, and outputting a reference clock. CONSTITUTION:An input data pulse is inputted to a PLL 1 and a lock detecting circuit 2, and the circuit 2 detects the lock state of the PLL 1 based on a read out control signal, a read out signal, and a regenerated clock. Further, the PLL 1 follows up the read out signal of a recording medium and regenerates and outputs the clock. Further, a lock monitoring circuit 5 monitors the lock operation of the PLL 1 based on a signal synchronizing with the read out control signal, the operation, and the output signal of the circuit 2. When the abnormality occurs in the regenerated clock of the PLL 1, the PLL 1 is switched to a selector 3, and the reference clock is sent from a reference clock generator 4 as the system clock. Thus, the deviation of timing can be suppressed to the minimum.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a clock regeneration circuit, and more specifically, to improving the characteristics of a clock regeneration circuit that regenerates a clock from a signal read from a recording medium such as an optical disk or a magnetic disk. Regarding.

<Prior Art> FIG. 4 is a block diagram showing an example of a conventional clock recovery circuit. In the figure, 1 is a PLL that reproduces and outputs a clock that follows input data pulses (hereinafter referred to as read signals) read from a recording medium such as an optical disk or a magnetic disk so that the frequency and phase match. 2 is a lock detection circuit, which receives a read control signal RDG.
ATE, PLL based on the read signal input to PLL1 and the reproduced clock output from PLLI.
Detects the locked state of I. 3 is a selector which selectively outputs the reproduced clock of the PLLI and the reference clock manually inputted from the reference clock generator 4 as the system clock according to the output signal of the lock detection circuit 2.

FIG. 5 is a timing chart illustrating the operation of the conventional circuit shown in FIG. 4. (A) is an output signal of an optical disc, in which one track is divided into multiple units called sectors by a gap (GAP) part, and the beginning part of each sector contains a preformat part containing the track number and sector number. is provided, followed by a data section with a gap section in between. RDGAT shown in (b)
The E signal becomes active only when reading the preformat part and data part of the output signal of the optical disc shown in (a), and becomes non-active in other gap parts. (c)
is a lock detection signal, which reads an input data pattern using a regenerated clock, and when a certain repeated pattern is continuously detected, it is determined that the device is locked and is output. Note that such a lock detection operation is performed only when the RDGATE signal is active.

(D) is a system clock output from the selector 3. The system clock is important for determining the timing of the entire system, and operates, for example, a data modulation/demodulation circuit. A normal reproduction clock is output during reading as shown in (2), and a reference clock is output during other writing as shown in (2). A lock detection signal is used for such lock switching.

<Problems to be Solved by the Invention> However, with this configuration, when the RDGATE signal is activated to read data, it is possible that noise or the like may accidentally lock onto the binarized data. be.

The clock reproduced and output from the PLL in such a state does not follow the input data pulse, and if used as a system clock, all the timings will be out of order, making it impossible to read even the next normal sector.

The present invention has been made with attention to these points,
The purpose is to provide a clock recovery circuit that can minimize timing errors that occur when the PLL locks in an abnormal state.

Means for Solving the Problems> The present invention to solve the above problems includes a PLL that reproduces and outputs a clock that follows a read signal from a recording medium, and a read control signal, a read control signal, a read signal, and a reproduced clock. a lock detection circuit that detects a lock state; and a lock detection circuit that detects a lock state;
a lock monitoring circuit for monitoring the locking operation of the PLL; and a selector for selectively outputting the recovered clock and the reference clock of the PLL according to the output signal of the lock monitoring circuit and the output signal of the lock detection circuit, The feature is that the selector outputs a reference clock when the operation is abnormal.

Effect> The clock recovery circuit of the present invention immediately switches the selector when the PLL is locked in an abnormal state, so that the reference clock is output from the selector. This allows system clock errors to be minimized.

<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and parts common to those in FIG. 4 are designated by the same reference numerals, and redundant explanation thereof will be omitted. In the figure, 5 is a lock monitoring circuit and an output signal of the lock detection circuit 2.

The lock operation of the PLLI is monitored based on the read control signal RDGATE and a signal (for example, 5YNC) synchronized with the read operation. 6 is an AND gate, and one input terminal receives the output signal of the lock detection circuit 2.
The output signal of the lock monitoring circuit 5 is input to the other input terminal, and the output terminal is connected to the control signal input terminal of the selector 3.

FIG. 2 is a block diagram showing a specific example of the lock monitoring circuit 5. As shown in FIG. In the figure, 7 is a D-type flip-flop;
The output signal of the lock detection circuit 2 is inputted to the data terminal, the 5YNC signal is inputted to the clock terminal, and the control signal RDGATE is inputted to the clear terminal via the inverter 8. 9 is a mono multi-by break,
RDGAT [E signal is manually operated. 10 is a NOR gate, and a D-type flip-flop 7 is connected to the first input terminal.
The output signal Q of the mono multi-bi-break 9 is input to the second input terminal, and the preformat area signal is input to the third input terminal.

11 is an AND gate, and one input terminal has RDG.
The ATE signal is input, and the output signal of the NOR gate 10 is input to the other input terminal.

Here, the 5YNC signal is a signal written at the beginning of the data section, and is used to synchronize data reading. P depends on whether the 5YNC signal is detected correctly or not.
Determine whether the lock of LL1 is normal or abnormal. That is,
Even if the lock detection signal is output, if the 5YNC signal cannot be detected, the PLL 1 determines that the system is erroneously locked, and switches the system clock to the reference clock output from the reference clock generator 4.

FIG. 3 is a timing chart showing the operations of FIGS. 1 and 2. (A) is the output signal of the optical disc, showing two sectors. In the first sector, the 5YNC signal shown in (D) is detected, indicating a normal state, and in the second sector, the 5YNC signal is detected. Indicates an undetected abnormal condition.

Mono multi-by-break 9 is RDGATE shown in (b)
Triggered by signal becoming active, (ch)
Outputs a pulse with a constant time width as shown in . If the PLLI is locked while this pulse is being output, the lock detection signal shown in (c) becomes H level. The preformat area signal shown in (g) becomes H level only while the preformat section is being output as an output signal of the optical disc. As shown in (W), the D-type flip-flop 7 latches the lock detection signal when the 5YNC signal is input, but does not latch the lock detection signal when the 5YNC signal is not input. The presence or absence of the 5YNC signal is determined based on whether or not the lock detection signal is latched.

While the mono multivibrator 9 is outputting a pulse with a fixed time width, the PLLI is locked and the 5YNC signal is detected, so the output signal of the OR gate 10 becomes H.
The output signal of the AND gate 11, that is, the output signal of the lock monitoring circuit 5 also remains at the H level as shown in (e). The output signal of AND gate 11 is RDGA after the RDG ATE signal becomes active.
Since the TE signal is kept at H level until it becomes non-active, the AND gate 6 outputs the H level lock detection signal shown in (c) as the control signal for the selector 3 shown in (f). .

On the other hand, if the 5YNC signal is not detected while the mono multi-by-break 9 outputs a pulse with a fixed time width, the AND gate 11 is immediately closed.
The control signal for the selector 3 output from the AND gate 6 becomes L level.

When the control signal of the selector 3 goes to H level, the selector 3 outputs the reproduced clock as the system clock, and when the control signal of the selector 3 goes to the L level, the selector 3 outputs the reference clock as the system clock.

In the above embodiment, the 5YNC signal was used as a condition for determining the normality of the locking operation of the PLLI.
The signal is not limited to the C signal, and a similar signal may be used depending on the format of the data to be written on the disk.

Further, in addition to the digital signal, it may be possible to directly monitor the RF multiplied signal and determine that the signal is normal if the amplitude is above a predetermined level.

<Effects of the Invention> With this configuration, when the PLL locks, it is determined whether the lock is normal or abnormal without immediately switching the system clock. It is possible to prevent malfunctions in the system caused by locking to noise and switching the system clock to a random recovered clock.

In addition, even if data has been successfully written to a sector, if the writing is insufficient and the 5YNC signal cannot be detected, there is still concern about the accuracy of the recovered clock, but this is also considered a lock malfunction. By switching to the clock, you can maintain the stability of the system clock.

As described in detail above, according to the present invention, it is possible to provide a clock regeneration circuit that can minimize timing errors that occur when the PLL is locked in an abnormal state.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
3 is a timing chart explaining the operation of FIG. 2, FIG. 4 is a block diagram showing an example of the conventional circuit, and FIG. 5 is a block diagram of the lock monitoring circuit shown in FIG. It is a timing chart explaining operation. 1...PLL 2...Lock release circuit 3...Selector 4...Reference clock generator 5...Lock monitoring circuit 6゜7...D type flip-flop 8...Inverter 9.・・Mono multi vibrator 10・or gate 11・and gate

Claims (1)

[Scope of Claims] A PLL that reproduces and outputs a clock that follows a read signal from a recording medium; A lock detection circuit that detects a locked state of the PLL based on a read control signal, a read signal, and a reproduced clock; and the lock. a lock monitoring circuit that monitors a lock operation of the PLL based on an output signal of a detection circuit, a read control signal, and a signal synchronized with a read operation; 1. A clock regeneration circuit comprising: a selector for selectively outputting a regenerated clock and a reference clock, the selector outputting the reference clock when the locking operation of the PLL is abnormal.