JPH02143464A - Manufacture of non-volatile memory - Google Patents

Abstract

PURPOSE:To make a memory cell highly integrated and densified by a method wherein a field oxide film is formed in self-alignment with a floating gate FG to eliminate the lamination thereof likewise source.drain are provided in self-alignment with the FG to be buried in the part below the field oxide film. CONSTITUTION:A gate oxide film 4, a doped poly Si 8, a buffer thermooxide film 9, an Si3N4 film 10, an SiO2 film 11 are laminated on a p type Si substrate 1. First, a resist mask 12 is formed on the film 11 to put up an FG by etching process and then the mask 12 is removed. Secondly, another resist mask 13 is formed after a specific pattern and then As ions are implanted to be covered with Si-made sidewall spacer 14. Thirdly, the other resist mask 15 in a specific shape is formed and then B ions are implanted to provide a p type channel stop. Fourthly, the mask 15 and the SiO2 film 11 are etched away and the substrate 1 is thermooxidized to form a field oxide film 2 by self-alignment with the FG so that a P<+> channel stop 3, n<+> source.drain 6, 7 may be formed on the lower part. Finally, the Si3N4 mask 10, the buffer SiO2 film 9 are etched away to stripe a poly Si made control gate CG 16 to complete the title memory.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing nonvolatile memory, and in particular, to a method for manufacturing nonvolatile memory.
P ROM (Erasable and Prog
rammableRead 0nly MeIIlor
It is suitable for application to the production of y).

[Summary of the invention]

The present invention is a method for manufacturing a nonvolatile memory having a plurality of memory cells having a structure in which a control gate is stacked on an island-shaped floating gate, in which a floating gate and a field oxide film are formed in a self-aligned manner.

The source region and drain region can be formed in a self-aligned manner with respect to the floating gate. These source and drain regions may be buried under the field oxide. According to the present invention, it is possible to achieve high integration density of memory cells.

[Conventional technology]

Conventionally, an ultraviolet erase type EFROM as shown in FIG. 19 has been known. As shown in Figure 19, this conventional EF
In a ROM, a field oxide film 102 such as a SiO□ film is selectively formed on the surface of a semiconductor substrate 101 such as a p-type silicon (St) substrate, thereby providing isolation between elements. A p-type channel stop region 103, for example, is formed under the field oxide film 102. Further, a gate insulating film 104 such as a Si film is formed on the surface of the active region surrounded by the field oxide film 102, and an island-shaped floating gate FC is formed on this gate insulating film 104. .

An interlayer insulating film 105 such as a Sin film is formed on this floating gate FGO, and this inter-glabellar insulating film 10
A control gate CG is formed above 5. On the other hand, in the middle part of the active region, n' type source and drain regions (not shown) are formed in portions corresponding to both sides of the floating gate FG.

Note that an EFROM has been proposed in which the memory cells are highly integrated by burying the source and drain regions under the field oxide film (Nikkei Electronics, April 4, 1988, no. 444). p
p, 151-157).

[Problem to be solved by the invention]

In the conventional EFROM shown in FIG. 19 described above, since the floating gate FG and the field oxide film 102 are not formed in a self-aligned manner, there is a distance a between the floating gate FC and the field oxide film 102. Overlapping occurs, which has been an obstacle to increasing the integration density of memory cells.

Accordingly, an object of the present invention is to provide a method for manufacturing a nonvolatile memory that can achieve a high integration density of memory cells.

Another object of the present invention is to provide a method for manufacturing a non-recurring memory that can prevent narrow channel effects.

[Means for Solving the Problems] In order to achieve the above object, a first invention of the present invention includes a control gate (CG) extending in a first direction on an island-shaped floating gate (FC). A method for manufacturing a non-stable memory having a plurality of memory cells in a stacked structure includes a step of forming an island-shaped floating gate (FG) on which an oxidation-resistant film (10) is formed; forming a first mask (13) covering the floating gate (FC) and extending in a second direction;
a step of performing ion implantation for forming a source EL region (6) and a drain region (7) using a mask (13); forming a second mask (15);
Channel stop region (3) using mask (15) of
A process of performing ion implantation for formation, a process of performing selective oxidation using the oxidation-resistant film (10) as an oxide mask, and a process of forming a control gate (CG) on the island-shaped floating gate (FC) via an insulating film (5). ).

The second aspect of the present invention is the nonvolatile memory manufacturing method described at the beginning, in which an oxidation-resistant film (10) is formed and a striped floating gate (FC) extending in the second direction is provided. ) and the process of forming an oxidation-resistant film (1
0) and striped floating gate (FG)
A step of performing ion implantation for forming the channel stop region (3) using the oxidation-resistant film (10) as a mask, a step of performing selective oxidation using the oxidation-resistant film (10) as an oxidation mask, and a step of performing selective oxidation using the oxidation-resistant film (10) as an oxidation mask;
G) Forming process and control game) (CG)
Striped floating game as a mask)
A step of forming an island-shaped floating gate (FC) by etching the source region (FC) and a step of forming an island-shaped floating gate (FC) by etching the source region (FC).
) and a step of performing ion implantation for forming the drain region (7).

A third aspect of the present invention is a nonvolatile memory manufacturing method described at the beginning, in which an oxidation-resistant film (10) is formed and a striped floating gate (FG) extending in the first direction is provided. ), a step of performing ion implantation for forming a channel stop region (3) using the striped floating gate (FC) as a mask, and a step of performing a first selective oxidation using the oxidation-resistant film (10) as an oxidation mask. A mask (19) extending in the second direction is formed, and a striped floating gate (FC) and a field oxide film (FC) formed by the first selective oxidation are formed using this mask (19). 2) to form an island-shaped floating gate (FC), selectively removing the field oxide film (2), and etching the source region (6) and drain region using a mask (19). (7) A step of performing ion implantation for formation, a step of performing second selective oxidation using the oxidation-resistant film (10) as an oxidation mask, and a step of forming a control gate (CG).

A fourth aspect of the present invention is the nonvolatile memory manufacturing method described at the beginning, on which an oxidation-resistant film (10) is formed and a striped floating gate extending in the second direction ( FC), a step of performing ion implantation for forming the source region (6) and drain region (7) using the striped floating gate (FC) as a mask, and a step of performing ion implantation for forming the source region (6) and drain region (7), and using the oxidation-resistant film (10) as an oxidation mask. Step of performing first selective oxidation and control gate CC
G> and forming a striped floating gate (CG) using the control gate (CG) as a mask.
FC) to form an island-shaped floating gate (FG) and a channel stop region (3) using the control gate (CG) as a mask.
The method includes a step of performing ion implantation for formation, and a step of performing second selective oxidation using the oxidation-resistant film (10) as an oxidation mask.

A fifth aspect of the present invention is the nonvolatile memory manufacturing method described at the beginning, in which an oxidation-resistant film (10) is formed and a striped floating gate (FC) extending in the second direction is provided. ), a step of performing ion implantation for forming the source region (6) and drain region (7) using the striped floating gate (FC) as a mask, and a step of performing ion implantation for forming the source region (6) and drain region (7) using the oxidation-resistant film (10) as an oxidation mask. Step 1 of performing selective oxidation, forming a mask (18) extending in the first direction, and using this mask (18), a striped floating gate (FG) is formed by the first selective oxidation. By etching the field oxide film (2), an island-shaped floating gate (F
G), selectively removing the field oxide film (2), performing ion implantation for forming the channel stop region (3) using the mask (18), and forming the oxidation-resistant film (10). ) as an oxidation mask, and a step of forming a control gate (CC).

A sixth aspect of the present invention is that in the first to fifth aspects, after forming a side wall spacer (14) on the side wall of the floating gate (FC), the channel stop region (
3) Perform ion implantation for formation.

[Effect]

According to the first invention, the field oxide film (2) can be formed in a self-aligned manner with respect to the floating gate (F(1,)) by selective oxidation. The overlap between the films (2) can be almost completely eliminated.Also, the source region (6) and drain region (7) can be buried under the field oxide film (2), and these source regions (6) and the drain region (7) can be formed in a self-aligned manner with respect to the floating gate (FC).

According to the second invention, the field oxide film (2) can be formed in a self-aligned manner with respect to the floating gates (FC).
The overlapping between C) and the field oxide film (2) can be made almost completely.Furthermore, the floating gate (FC) can be formed in self-alignment with the control gate (CC).

According to the third invention, since the field oxide film (2) can be formed in a self-aligned manner with respect to the floating gates (FC), these floating gates) (
FC) and the field oxide film (2) can be almost completely eliminated. In addition, the source region (6) and drain region (7) can be buried under the field oxide film (2), and these source regions (
6) and the drain region (7) as a floating gate (
FG) in a self-aligned manner.

According to the fourth invention, since the field oxide film (2) can be formed in a self-aligned manner with respect to the floating gates (FC), these floating gates 1-
(FC) and the field oxide film (2) can be almost completely eliminated. Also, source area (6)
and field oxidation 111 (2) of the drain region (7)
The source region (6) and drain region (7) can be formed in a self-aligned manner with respect to the floating gate (FC). Furthermore, the floating gate (FG) can be formed in self-alignment with the control gate (CG).

According to the fifth invention, since the field oxide film (2) can be formed in a self-aligned manner with respect to the floating gates (FC), these floating gates (F
C) and the field oxide film (2) can be almost completely eliminated. Further, the source region (6) and the drain region (7) can be buried under the field oxide film (2), and the source region (6) can be buried under the field oxide film (2).
) and drain region (7) as a floating gate (F
C) can be formed in a self-aligned manner. Furthermore, the floating gate (FC) can be formed in self-alignment with the control gate (CG).

According to the sixth invention, the amount of wraparound of the channel stop region (3) below the floating gate (FC) can be reduced.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. The following four embodiments all show embodiments in which the present invention is applied to the manufacture of an ultraviolet erasable EPROM. In all the figures of the embodiments, parts having the same functions are given the same reference numerals.

Figure 1 is a plan view of the main parts of an EPROM according to the embodiment (2) of the present invention, Figure 2 is a cross-sectional view taken along the line (2)--(2) in Figure 1, and Figure 3 is the same as that in Figure 1. Figure 4 is a cross-sectional view taken along the line IV--IV in Figure 1. Figure 5 is a cross-sectional view taken along the line V-V in Figure 1. .

As shown in FIGS. 1 to 5, the EF according to this embodiment I
In a ROM, a field oxide film 2 such as a SiO□ film is selectively formed on the surface of a semiconductor substrate 1 such as a p-type St substrate, thereby providing isolation between elements. Under this field oxide film 2, a p-type channel stop region 3, for example, is formed.

Further, a gate insulating film 4 such as a SiO□ film is formed on the surface of the active region surrounded by the field oxide film 2, and a polycrystalline Si film doped with impurities is formed on the gate insulating film 4, for example. An island-shaped floating gate FG made of such a conductor film is formed.

This floating gate FG has, for example, a substantially square planar shape. A glabellar insulating film 5 such as a Si0g film is formed on the floating gate FC. Note that, as this interlayer insulating film 5, for example, 5
It is also possible to use a three-layer structure film consisting of i02 film/Si3N film and film/SiO2 film. The symbol CG indicates a control gate made of a conductive film such as a polycrystalline Si film doped with impurities. Note that this control gate CG can also be formed of, for example, a polycide film (a film with a two-layer structure in which a high melting point metal silicide film is layered on a polycrystalline Si film doped with impurities).

On the other hand, field oxidation 11! In the semiconductor substrate 1 below J 2 , for example, an n-type source region 6 and drain region 7 are formed. That is, these source region 6 and drain region 7 are buried under field oxide film 2. Further, these source region 6 and drain region 7 are formed in a self-aligned manner with respect to the floating gate FC. Note that these source region 6 and drain region 7 may be formed at opposite positions.

Next, a method for manufacturing an EFROM according to this embodiment (2) will be explained. FIGS. 6A to 6E show the manufacturing method in order of steps. Note that the left and right figures in FIGS. 6A to 6E show cross-sectional views taken along the lines 1--2 and 1-2 in FIG. 1, respectively.

As shown in FIG. 6A, first, a gate insulating film 4 such as a SiOg film is formed on the entire surface of the semiconductor substrate 1 by, for example, thermal oxidation. Next, after forming, for example, a polycrystalline Si film 8 on this gate insulating film 4 by, for example, the CVD method, this polycrystalline Si film 8 is doped with impurities to lower its resistance.

Next, a buffer SiO□ film 9 is formed on the surface of this polycrystalline Si film 8 by, for example, thermal oxidation. Next, the entire surface of this buffer SiO□ film 9 is coated with, for example, Si by, for example, the CVD method.
3N to form film 10. Next, this 5LNa film IO
For example, a SiO□ film 11 is deposited on the entire surface by, for example, the CVD method, and then a resist pattern 12 having a predetermined shape corresponding to the shape of the floating gate FC is formed on the 5i02 film 11 by lithography. In addition, SiO
□Membrane 11 Can be omitted depending on the membrane type 1.

Next, using this resist pattern 12 as a mask, SiO
□ Film 11

As a result, an island-shaped floating gate FC is formed as shown in FIG. 6B. Next, a planar resist pattern 13 as shown in FIG. 1 is formed so as to cover this laminated film of a predetermined shape, and then, using this resist pattern 13 as a mask, a source region such as arsenic (As), etc. An n-type impurity for forming a drain region is ion-implanted into the semiconductor substrate 1 at a high concentration (the n-type impurity implanted into the semiconductor substrate 1 is represented by . . . ). After this, this resist pattern 13 is removed.

Next, after forming, for example, a polycrystalline Si film on the entire surface by, for example, a CVD method, this polycrystalline Si film is anisotropically etched in a direction perpendicular to the substrate surface by, for example, a reactive ion etching (RIE) method. 6C, sidewall spacers 14 are formed. Note that this sidewall spacer 14 can also be formed by, for example, forming a SiO□ film over the entire surface and anisotropically etching it. Next, after forming a planar resist pattern 15 as shown in FIG. 1, a channel stop region such as boron (B) is formed using this resist pattern 15, the sidewall spacer 14, and the above-described laminated film as a mask. ion implantation of p-type impurities into the semiconductor substrate 1 (the p-type impurities implanted into the semiconductor substrate 1 are
After that, this resist pattern 15 is removed, and the SiO2 film 11 is also etched away.

Next, by selectively thermally oxidizing the semiconductor substrate 1 using the 5i3Na film 10 as an oxidation mask, the field oxide film 2 is formed into a floating gate FG as shown in Figure 6.
Formed in a self-consistent manner. During this thermal oxidation,
The implanted impurities are electrically activated and diffused in the depth direction to form channel stop region 3 and source MMi6 and drain regions 7 under field oxide M2. After this, Si, N, film 10 and buffer S
in.

The film 9 is sequentially etched away.

Next, as shown in FIG. 6, after a glabellar insulating film 5 such as a SiO□ film is formed on the entire surface by, for example, the CVD method, a polycrystalline Si film 16 doped with impurities, for example, is formed on the glabellar insulating film M5. form. Thereafter, this polycrystalline Si film 16 is patterned into stripes by etching to form control gates CG. As a result, as shown in FIGS. 1 to 5, the target EPROM
is completed.

As described above, according to this embodiment (2), after forming the island-shaped floating gate FC on which Si3N as an oxidation-resistant film and film IO are formed, this SixN4
Since the field oxide film 2 is formed by performing selective oxidation using the film 10 as an oxidation mask, the field oxide film 2 can be formed in a self-aligned manner with respect to the floating gate (FG). Therefore, the overlap between floating gate FG and field oxide film 2 can be almost completely eliminated. Further, the source region 6 and drain region 7 can be buried under the field oxide film 2, and these source region 6 and drain region 7 can be formed in a self-aligned manner with respect to the floating gate FC. Furthermore, since the field oxide film 2 is formed by performing selective oxidation after forming the sidewall spacer 14 on the side wall of the floating gate FG, the length of the bird's beak at the end of the field oxide film 2 is reduced. be able to. As a result, the area occupied by each memory cell can be reduced, so that the memory cells can be integrated at a high density.

Further, since the p-type impurity ion implantation for forming the channel stop region is performed after forming the sidewall spacer 14, the amount of wraparound of the channel stop region 3 below the floating gate FC can be reduced. This can prevent narrow channel effects.

Fig. 7 is a plan view of the main parts of the EPROM according to the embodiment (2) of the present invention, Fig. 8 is a cross-sectional view taken along the line - - - of Fig. 7, and Fig. 9 is a plan view of the main part of the EPROM according to the embodiment (2) of the present invention. A sectional view taken along the line IX-IX is shown.

As shown in FIGS. 7, 8 and 9, this embodiment
In the EFROM according to the present invention, a floating gate FC is formed in a self-aligned manner with respect to a field oxide film 2. This floating gate FC is formed in a self-aligned manner with respect to the control gate CG. Further, a source region 6 and a drain region 7 are formed in self-alignment with respect to the floating gate FG.

These source regions 6 and drain regions 7 are similar to those in Example I.
Unlike the field oxide film 2, it is not buried under the field oxide film 2.

Next, a method for manufacturing an EFROM according to this embodiment (2) will be explained.

As shown in FIG. 10A, first, in the same manner as in Example I, a gate insulating film 4, a polycrystalline Si film 8, a buffer Sio! Membrane 9.513Na membrane 10.5to21F
After sequentially forming J11, a resist pattern 17 having a planar shape as shown in FIG. 7 is formed on this 5 inz film 11.

Next, using this resist pattern 17 as a mask, 5iO
t film 11, Si3 N4 film 10, buffer SiO□ film 9
The laminated film consisting of the polycrystalline Si film 8 and the polycrystalline Si film 8 is sequentially etched into a striped shape as shown in FIG. 10B. After this, the resist pattern 17 is removed. next,
After forming a sidewall spacer 14 made of polycrystalline Si or SiO2 in the same manner as in Example 2, using this sidewall spacer 14 as a mask, a P-type impurity such as B for forming a channel stop region is injected into the semiconductor substrate 1. ion implantation. Thereafter, the Sin film 11 is removed by etching.

Next, field oxide film 2 is formed by performing selective oxidation using 5izNn film 10 as an oxidation mask. At this time, a channel stop region 3 is formed under this field oxide film 2.

Next, for example, after a polycrystalline Si film doped with impurities is formed over the entire surface, this polycrystalline Si film is patterned into a predetermined shape by etching to form a control gate CG as shown in FIG.

Next, by etching the striped floating gate FC using this control gate CG as a mask, an island-shaped floating gate FG is formed. Next, by ion-implanting n-type impurities such as As into the semiconductor substrate 1 using these control gates CG and floating gates FG as masks, a self-aligned structure is formed with respect to these control gates CG and floating gates FC. A source region 6 and a drain region 7 are formed. As a result, Figures 7 and 8
The target EPROM is completed as shown in FIG. 9 and FIG.

As described above, according to this embodiment H, as in embodiment I, the floating gate FC and the field oxide film 2
The overlap between them can be almost completely eliminated, and the source region 6 and drain region 7 can be formed in self-alignment with respect to the floating gate 1-FC. Furthermore, since the sidewall spacer 14 is formed, the length of the bird's beak at the end of the field oxide film 2 can be reduced.In addition, the floating gate can be self-aligned with respect to the control gate CG. FC can be formed.Thus, a high integration density of memory cells can be achieved.-0 Furthermore, as in Example I, there is also an advantage that narrow channel effects can be prevented.

Figure 11 is a plan view of the main parts of an EFROM according to the embodiment (1) of the present invention, Figure 12 is a cross-sectional view taken along the xm-xm line in Figure 11, and Figure 13 is the same as in Figure 11. A sectional view taken along the line Xm-Xm is shown.

As shown in FIGS. 11, 12, and 13, the EFROM according to the embodiment (2) is different from the EFROM according to the embodiment (2).
It has a similar configuration.

Next, a method for manufacturing an EFROM according to this embodiment (2) will be explained. 14A to 14F show the manufacturing method in the order of steps. In addition, in FIGS. 14A to 14F, the left and right diagrams are the xm-xm line and the xm-
A cross-sectional view along the Xm line is shown.

As shown in FIG. 14A, first, a gate insulating film 4, a polycrystalline Si film 8, a buffer 'SiO□ film 9 are formed on a semiconductor substrate 1.
and 5iiN4 film 10, this 5ixN
A resist pattern 18 having a planar shape as shown in FIG. 1L is formed on the a film 10.

Next, using this resist pattern 18 as a mask, St.
N, film 10, buffer SiO□ film 9, polycrystalline Si film 8
The laminated film consisting of the gate insulating film 4 and the gate insulating film 4 is sequentially etched to form a striped shape as shown in FIG. 14B. After this, the resist pattern 18 is removed. Next, a sidewall spacer 14 made of polycrystalline Si or SiO□ is formed in the same manner as in Examples ① and ②, and then a channel stop region such as B is formed in the semiconductor substrate I using the sidewall spacer I4 as a mask. A p-type impurity for formation is ion-implanted.

Next, selective oxidation is performed using the Si3N film 10 as a mask to form a field oxide film 2 and a channel stop region 3 as shown in FIG. 14C.

Next, as shown in Figure 14, after forming a resist pattern 19 having a planar shape as shown in Figure 11, using this resist pattern 19 as a mask, the above-described laminated film and field oxidation Pt2 are selectively etched. . As a result, an island-shaped floating gate FG is formed. Next, using this resist pattern 19 and the above-described laminated film as a mask, ions of an n-type impurity such as As for forming a source region and a drain region are implanted into the semiconductor substrate 1. After this, the resist pattern 19 is removed.

Next, by performing selective oxidation again using the Si3N film 10 as a mask, a field oxide film 2 is formed around the floating gate FC, as shown in FIG. 14F.

After that, a control gate CG is formed to achieve the desired EFR as shown in FIGS. 11, 12, and 13.
Complete the OM.

According to this embodiment (2), similarly to embodiment I, it is possible to achieve a high integration density of memory cells and to prevent the narrow channel effect.

Fig. 15 is a plan view of the main part of the EFROM according to the embodiment (1) of the present invention, Fig. 16 is a sectional view taken along the line xvi-x (2) in Fig. 15, and Fig. 17 is A sectional view taken along the line X■-X■ is shown.

As shown in FIGS. 15, 16, and 17, the EPROM according to this embodiment (2) is different from the EPROM according to embodiment H.
It has a similar configuration.

Next, a method for manufacturing an EPROM according to this embodiment (2) will be explained.

As shown in FIG. 18A, first, a gate insulating film 4, a polycrystalline Si film 8, a buffer SiO□ film 9.
After sequentially forming the 5in2 film 10 and the 5in2 film 11, a resist pattern 17 having a planar shape similar to that shown in FIG. 7 is formed on the 5i02 film 11.

Next, using this resist pattern 17 as a mask,
g film 111St3 Ng film 10, buffer SiO□Jl
The laminated film consisting of the polycrystalline Si film 19 and the polycrystalline Si film 8 is sequentially etched into a striped shape as shown in FIG. 18B. Next, after removing the resist pattern 17, a Sin film is formed on the side surface of the striped floating gate FG by thermal oxidation, for example. Next, for example, Si3
A N film 20 and a polycrystalline Si film 21 are sequentially formed over the entire surface.

Next, these polycrystalline Si film 21 and 5tzN4 film 20
For example, by anisotropically etching by RIE method, the 18th
As shown in FIG. C, a sidewall spacer 14 made of polycrystalline St is formed, and the Si3N4 film 20 is left only on the sidewall spacer 14. Thereafter, using the sidewall spacer 14 and the above-described laminated film as a mask, a P-type impurity such as B for forming a channel stop region is ion-implanted into the semiconductor substrate 1.

Next, the sidewall spacer 14 and the SiO2 film 11
One layer on the film is removed to obtain the state shown in the 18th diagram.

Next, selective oxidation is performed using the Si3N4 films 10 and 20 as a mask to form a field oxide film 2 and a channel stop region 3, as shown in FIG.

Next, after removing the Si3N4 film 10.20 by etching, a control gate CG is formed. Next, by masking this control game (CG) and etching the striped floating game (FC),
An island-shaped floating gate FG is formed. As a result, the intended EPROM is completed as shown in FIGS. 15, 16, and 17.

According to the embodiment (2), in addition to the same advantages as the embodiment (2), there are the following advantages. That is, as shown in FIG. 18C, the side walls of the floating gate FC are
Since the film 20 is formed, the wraparound of the field oxide film 2 into the active region can be almost completely eliminated, and therefore, it is possible to achieve even higher integration density of memory cells. Further, since the wraparound of the channel stop region 3 below the floating gate FG can be almost completely eliminated, the narrow channel effect can be prevented even more effectively.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications can be made based on the technical idea of the present invention.

For example, in Example 2, the floating gate F
Although C is formed in a self-aligned manner with respect to the control gate CG, it is not necessary to do so. Furthermore, in Example 2, the order of ion implantation for forming the source region and drain region and ion implantation for forming the channel stomp region can be changed.

〔Effect of the invention〕

Since the present invention is configured as described above, the following effects can be obtained.

According to the first to fifth inventions, it is possible to achieve high integration density of memory cells.

According to the sixth invention, it is possible to achieve high integration density of memory cells and to prevent narrow channel effects.

[Brief explanation of the drawing]

FIG. 1 is a plan view of the main parts of an EPROM according to the embodiment (2) of the present invention, FIG. 2 is a sectional view taken along the line (■--) in FIG. 1, and FIG. 3 is a cross-sectional view taken along the line (--) in FIG. 4 is a sectional view taken along line IV-IV in FIG. 1, FIG. 5 is a sectional view taken along line V-V in FIG. 1, and FIGS. FIG. 6E is a sectional view showing the manufacturing method of EFROM according to Example I of the present invention in the order of steps, and FIG. 7 is a cross-sectional view of the EPRO according to Example H of the present invention.
FIG. 8 is a sectional view taken along the line ■-■ in FIG. 7, FIG. 9 is a sectional view taken along the line IX-IX in FIG. 7, and FIG. 10 A and FIG. 10B is a sectional view showing the EFROM manufacturing method according to the embodiment (1) of the present invention in the order of steps.
1 is a plan view of the main parts of an EPROM according to the embodiment ① of the present invention, FIG. 12 is a sectional view taken along the xn-xm line in FIG. 11, and FIG. 13 is a sectional view taken along the xm-xm line in FIG. 11. 14A to 14E are cross-sectional views showing the manufacturing method of an EPROM according to the embodiment (2) of the present invention in order of process, and FIG. 15 is a cross-sectional view showing the main parts of the EPROM according to the embodiment (2) of the present invention. Plan view,
Fig. 16 is a sectional view taken along the line XVI-XVI in Fig. 15, Fig. 17 is a sectional view taken along the line X-XVII in Fig. 15, and Figs. 18A to 18E are the main Embodiment 1 of the EFROM manufacturing method according to the embodiment
FIG. 9 is a sectional view of the main parts of a conventional EFROM. Explanation of main symbols in the drawings 1: Semiconductor substrate, 2: Field oxide film, 3: Channel stomp region, 4: Gate insulating film, 5ki insulating film, 6: Source region, 7: Drain region, 8, 2
1: Polycrystalline Si film, 10.20: 5isNa film,
12. 13. 15. 17. 18.19 resist pattern, FG: floating gate, C
G: Control gate. Agent Patent Attorney Tadashi Sugiura Chi n-n line 2 side EPROM cross section ■-■ 碌Jli side G ■ line cross section of EFROM Figure 6 D ■-■ line J4 mountain n-m Eye cross section EPROMt＞ Urazo')'jL Fig. 6 E ■-■ Line 1fr mountain ■-■ Production capacity of EPROM Figure 14B 1-Tenmu slanting mountain U-' A Manufacturing method of EPROM 4 1(p) Back side of EPROM Figure 18 E Yoshi, Commissioner of the Japan Patent Office 1) Takeshi Moon 1, Indication of the case Patent Application No. 296859 of 1988 2, Name of the invention Non-volatile memory Manufacturing method 3゜Relationship with the case of the person making the amendment Patent applicant address: 6-7-35, Kitashinyo, Tokyo Parts Co., Ltd. Name (21
8) Sony Corporation Representative Director Norio Ohga 43 Agent 170 Address 1-48-10 Higashiikebukuro, Toshima-ku, Tokyo Juju system March 7, 1989 6, Subject of amendment 7, Content method of amendment (1) Amend the application as shown in the attached sheet. (2) Correct "Figure 14 E" on page 36, line 13 of the specification cylinder to "Figure 14 F."that's all

Claims (1)

[Claims] 1. A method for manufacturing a nonvolatile memory having a plurality of memory cells having a structure in which a control gate extending in a first direction is stacked on an island-shaped floating gate, forming a first mask covering the island-shaped floating gate and extending in a second direction; a step of performing ion implantation for forming a source region and a drain region using a first method;
a step of forming a second mask extending in the direction of and performing ion implantation for forming a channel stop region using the second mask; a step of performing selective oxidation using the oxidation-resistant film as an oxidation mask; A method for manufacturing a nonvolatile memory, comprising the step of forming the control gate on the island-shaped floating gate via an insulating film. 2. A method for manufacturing a nonvolatile memory having a plurality of memory cells having a structure in which a control gate extending in a first direction is stacked on an island-shaped floating gate, an oxidation-resistant film being formed thereon; a step of forming a striped floating gate extending in a second direction; a step of performing ion implantation for forming a channel stop region using the oxidation-resistant film and the striped floating gate as a mask; performing selective oxidation using the film as an oxidation mask; forming the control gate; etching the striped floating gate using the control gate as a mask to form the island-shaped floating gate; 1. A method of manufacturing a nonvolatile memory, comprising the step of performing ion implantation for forming a source region and a drain region. 3. A method for manufacturing a nonvolatile memory having a plurality of memory cells having a structure in which a control gate extending in a first direction is stacked on an island-shaped floating gate, an oxidation-resistant film being formed thereon; and forming a striped floating gate extending in the first direction; performing ion implantation for forming a channel stop region using the striped floating gate as a mask; and using the oxidation-resistant film as an oxidation mask. forming a mask extending in a second direction, and using this mask to remove the striped floating gate and the field oxide film formed by the first selective oxidation; forming the island-shaped floating gate by etching and selectively removing the field oxide film; performing ion implantation for forming source and drain regions using the mask; 1. A method for manufacturing a nonvolatile memory, comprising the steps of: performing second selective oxidation using a oxide film as an oxidation mask; and forming the control gate. 4. A method for manufacturing a nonvolatile memory having a plurality of memory cells having a structure in which a control gate extending in a first direction is stacked on an island-shaped floating gate, an oxidation-resistant film being formed thereon; a step of forming a striped floating gate extending in a second direction; a step of performing ion implantation for forming a source region and a drain region using the striped floating gate as a mask; and oxidizing the oxidation-resistant film. a step of performing a first selective oxidation as a mask; a step of forming the control gate; and a step of etching the stripe-shaped floating gate using the control gate as a mask to form the island-shaped floating gate; A method for manufacturing a nonvolatile memory, comprising the steps of performing ion implantation for forming a channel stop region using the control gate as a mask, and performing a second selective oxidation using the oxidation-resistant film as an oxidation mask. . 5. A method for manufacturing a nonvolatile memory having a plurality of memory cells having a structure in which a control gate extending in a first direction is stacked on an island-shaped floating gate, an oxidation-resistant film being formed thereon; a step of forming a striped floating gate extending in a second direction; a step of performing ion implantation for forming a source region and a drain region using the striped floating gate as a mask; and oxidizing the oxidation-resistant film. a step of performing first selective oxidation as a mask, forming a mask extending in the first direction, and using this mask to oxidize the striped floating gate and the field oxidation formed by the first selective oxidation; forming the island-shaped floating gate by etching the film and selectively removing the field oxide film; performing ion implantation for forming a channel stop region using the mask; 1. A method for manufacturing a nonvolatile memory, comprising the steps of: performing second selective oxidation using a oxide film as an oxidation mask; and forming the control gate. 6. Claims 1 and 2, characterized in that ion implantation for forming the channel stop region is performed after forming sidewall spacers on the sidewalls of the floating gate.
6. The method for manufacturing a nonvolatile memory according to 3, 4 or 5.