JPH02143993A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To enable an interleave system to be employed and to heighten the output throughput of the system by providing an output circuit to hold readout data from a random access memory, etc., until it is established and to send it to the outside. CONSTITUTION:The output circuit DOB which holds the readout data from the random access memories RAM0-RAM3, etc., to be set at operating states next until the readout data from the random access memories RAM0-RAM3 are established and sends them to the outside is provided at a memory unit, etc., including plural random access memories RAM0-RAM3 set at the operating states alternatively according to corresponding start-up selecting signals CS0-CS3. Therefore, output contention by the plural random access memories, etc., can be prevented occurring. In such a way, it is possible to shorten the cycle time of the memory unit to a time almost equivalent to data holding time, and to heighten the output throughput.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device, for example,
The present invention relates to a technique that is particularly effective when used in a memory unit that includes a plurality of dynamic RAMs (random access memories) and uses an interleaving method.

[Conventional technology]

Dynamic RAM with faster access time
There is. Furthermore, there is a memory unit consisting of a plurality of such dynamic RAMs.

Further, as one means for improving the substantial output throughput of the memory unit, there is an interleaving method in which a plurality of dynamic RAMs are temporarily put into an overlapping operating state.

Dynamic RAM with faster access time
This is described, for example, in Japanese Patent Application No. 62-058809.

[Problem to be solved by the invention]

In the above interleaving method, a continuous series of addresses are sequentially assigned to a plurality of dynamic RAMs constituting a memory unit.

Therefore, when these addresses are sequentially accessed, the plurality of dynamic RAMs receive corresponding chip selection signals C3O-C33, as shown in FIG.
are sequentially set to a low level, thereby alternatively and sequentially being brought into an operating state. As a result, for example, after the first dynamic RAM becomes inactive, the second dynamic RAM can be duplicated without being aware of the cover time tRc required for precharging its complementary data line, etc. The actual throughput of the memory unit is improved.

However, the inventors of the present application have discovered that the above memory unit still has the following problems. That is, the plurality of dynamic RAMs constituting the memory unit are, for example, a so-called output dry state type in which the output is in a high impedance state when not selected, and their output terminals are connected to a common data output terminal po.
The logic form is directly connected to ut. Therefore, the read data output via the data output terminal Dout is
For example, after the first dynamic RAM is set to a non-selected state until the read data of the second dynamic RAM is established, output contention among these dynamic RAMs occurs, resulting in an unspecified state. therefore,
In order to ensure a predetermined data retention time tOH for the read data outputted via the data output terminal Dout, the cycle time tc of the memory unit must be set as tC>
It is necessary to set L [lH+ L AC . Here, t AC corresponds to the access time of the dynamic RAM.

As a result, even though the memory unit adopts the incremental method, it is prevented from increasing the cycle time, and its output throughput is limited.

An object of the present invention is to provide an efficient interleaving method for a memory unit including a plurality of dynamic RAMs, etc. Another object of the present invention is to speed up the cycle time of a memory unit employing an interleaving method and improve its output throughput.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, data read from each random access memory is transferred to a memory unit including a plurality of random access memories that are selectively activated according to the corresponding activation selection signal, and then transferred to a memory unit that includes a plurality of random access memories that are selectively activated according to the corresponding activation selection signal. An output circuit is provided to hold the read data until it is established and send it to the outside.

[For production]

According to the above-mentioned means, it is possible to prevent output contention among a plurality of random access memories, etc., so that the cycle time of the memory unit can be shortened to a time approximately equivalent to the data retention time, and the output throughput can be increased.

〔Example〕

FIG. 2 shows a memory unit MU to which the present invention is applied.
A block diagram of one embodiment is shown.

Further, FIG. 1 shows a circuit block diagram of an embodiment of the data output buffer (output circuit) DOB of the memory unit MU of FIG. 2, and FIG. 3 shows a circuit block diagram of an embodiment of the data output buffer (output circuit) DOB of the memory unit MU of FIG. A timing diagram of one embodiment of a read operation is shown. According to these figures, an overview of the configuration and operation of the memory unit l-MU of this embodiment as well as its characteristics will be explained. In addition, each circuit element in Fig. 1 and @2
The circuit elements constituting each block in the figure are formed on a semiconductor substrate of 1 (lla) such as single crystal silicon using known semiconductor integrated circuit manufacturing techniques, although not particularly limited thereto.

In FIG. 2, the memory unit MU includes, but is not particularly limited to, four random access memories (storage circuits) RAMO to RAM to which a series of addresses are sequentially assigned.
3 is the basic configuration. Although not particularly limited, these random access memories have a basic configuration of a memory array in which nMOS memory cells are arranged in a lattice pattern, and a peripheral circuit consisting of bipolar transistors and CMOS (complementary MO3FET). Each is configured with a CMOS dynamic RAM.

Although not particularly limited, the memory unit MU is supplied with a chimbu enable signal CE, a write enable signal WE, and i+l bit address signals AO to Ai from a memory control unit (not shown). this house,
The chip enable signal GE is supplied to the chip selection circuit C3L, and the write enable signal WE is commonly supplied to the random access memories RAM0 to RAM3. Also,
Of the address signals, the address signal AO of the lower two pins
and A1 are supplied to the chip selection circuit C3L as chip address signals CSO and cal, although not particularly limited, and the remaining i-1 bits of address signals A2 to At are
Address signals axQ to axj and Y address signal ayQ
~ayk as random access memory RAM0~RA
Commonly supplied to M3. Random access memory RA
Furthermore, 1-bit write data is commonly supplied to M0 to RAM3 via a data input terminal Din, although this is not particularly limited.

The chip selection circuit C3L receives the chip enable signal C3L.
By setting E to a low level, it is selectively put into an operating state. In this operating state, the chip selection circuit C8L decodes the chip address signals csO and csl, and outputs the corresponding chip selection signals (activation selection signals) CSO~
CS3 is alternatively set to low level. These chip selection signals τT1-CS3 are supplied to corresponding random access memories RAM0-RAM3.

Random access memory RAM0~RAM3LJ
:, a memory array consisting of nMOS memory cells arranged in a lattice pattern, bipolar transistors and CMOS
The basic configuration is a peripheral circuit consisting of: Random access memories RAM0 to RAM3 are connected to the chip selection circuit C3.
The corresponding chip selection signals τ11 to C33 are selectively brought to a low level by L, thereby being alternatively brought into an operating state. At this time, random access memory RAM0
~RAM3 is placed in a write mode when the write enable signal WE is at a low level, and placed in a read mode when the write enable signal WE is at a high level. As described above, the chip selection signals C3O to C33 are formed based on the chip address signals csQ and csl, that is, the lower two bits of the address signals AO and A1. As a result, a series of addresses designated by address signals AO to Ai are sequentially assigned to random access memories RAM0 to RAM3. Therefore, for example, when the address signals AO to Ai are counted up, the random access memories RAM0 to RAM3 are sequentially activated.

When the random access memories RAM0 to RAM3 are activated in write mode, one memory cell designated by the X address signals axQ to axJ and the Y address signals ayO to ayk is selected, and the data input terminal Writes the write data supplied via Din.

On the other hand, when the random access memories RAM0 to RAM3 are activated in the read mode, the X address signals axQ to axJ and the Y address signals ayQ to ayk are activated.
One memory cell designated by is set to a selected state, and read data corresponding to the stored data is output. At this time, the random access memories RAM0 to RAM3 output internal output signals doQ-w according to the read data.
d.

3 and a corresponding timing signal (output control signal) at the time when these read data are established.
φoeO to φoe3 are set to high level. Internal output signals doO-do3 and timing signals φoeQ to φo
e3 is supplied to the data output bath sofa (output circuit) DOB.

Although not particularly limited, the data output buffer DOB includes an output selection circuit SEL, an output latch OL, and an output drive circuit OD, as shown in FIG.

The output selection circuit SEL of the data output buffer DOB includes, but is not particularly limited to, Nant gate circuits 01 to G8. Among them, one input terminal of the Nant gate circuits G1 to G4 is connected to random access memories RAM0 to RAM3.
, the corresponding internal output signals doQ-wdo3 are respectively supplied, and one input terminal of the Nant gate circuits 05-G8 receives the corresponding internal output signals doO-do.
Inverted signals from three inverter circuits N1 to N4 are respectively supplied. Nant gate circuits 01 to N4 and N
The corresponding timing signals φoeO to φoe3 are commonly supplied to the other input terminals of the random access memories RAM0 to RAM3, respectively.

The output signals of the Nant gate circuits 01 to G4 are respectively supplied to the first to fourth input terminals of the Nant gate circuit G9. The output signal of the Nant gate circuit G9 is inverted by the inverter circuit N5 and then supplied as an inverted cent signal T to one input terminal of the Nant gate circuit Gll of the output lunch OL. Similarly, Nant gate circuit 05~
The output signal of G8 is supplied to the first to fourth input terminals of the Nant gate circuit GIO, respectively. After the output signal of the Nant gate circuit GIO is inverted by the inverter circuit N6, the output signal is sent to the output lunch OL as an inverted reset signal r.
is supplied to one input terminal of the Nant gate circuit G12.

The output lunch OL of the data output buffer DOB is composed of two Nant gate circuits 011 and G12 whose input terminals and output terminals are cross-connected to each other, although this is not particularly limited. As described above, one input terminal of these Nantes gate circuits is supplied with the inverted set signal S and the inverted reset signal r, respectively, and the other input terminal is supplied with the output of the paired Nantes gate circuits G12 and Gll. are cross-coupled to the respective terminals.

The output drive circuit OD of the data output buffer DOB is, although not particularly limited, the output M of an N-channel type Hllil provided in series between the power supply voltage and the ground potential of the circuit.
Contains O3FETQ1 and G2.

The output signals of the Nant gate circuits Gll and G12, that is, the internal signal od and the inverted internal signal od, are supplied to the gates of the MOS FETQ1 and G2, respectively. Additionally, the commonly coupled sources and drains of MOSFETs QL and G2 are further coupled to the data output terminal Dout.

When the random access memories RAM0 to RAM3 are activated in the read mode, one memory cell corresponding to the X address signals axQ to axj and the Y address signals ayO to ayk is first selected, as shown in FIG. state, and the internal output signal do according to the stored data
Q~do3 is output. Further, at the time when the levels of these internal output signals are established, the corresponding timing signals φoeQ to φoe3 are alternatively set to high level. At this time, if the corresponding internal output signal doO-do3 is at a high level, that is, logic '1'', the output signal of the corresponding Nantes gate circuit G1-04 is set to a low level, and the output signal of the Nantes gate circuit G9 is set to a high level. As a result, the inverted cent signal 3 becomes the timing signal φoeQ
~While φoe3 is set to high level, -temporarily set to low level. As a result, the output latch OL is set, and high-level read data is output to the data output terminal Dout.

On the other hand, when the timing signals φoeQ to φoe3 are alternatively set to high level, the corresponding internal output signals doQ to
When do3 is at a low level, that is, logic "01," the output signals of the Nant gate circuits 05 to G8 are alternatively set to a low level, and the output signal of the Nant gate circuit G10 is set to a high level.

As a result, the inverted recent signal r becomes the timing signal φo
While eQ to φoe3 are set to high level, -temporarily set to low level. As a result, the output lunch OL is brought into the re-cent state, and low-level read data is output to the data output terminal [) out.

By the way, once the output latch OL is brought into the set state or reset state, the output latch OL remains in the set state or reset state until the next time any of the random access memories RAM0 to RAM3 is put into the operating state in the read mode and the read data is established.
In other words, the timing (the set state or the reset state is maintained until any of the a-numbers φoeQ to φoe3 is set to high level next time. In other words, in this embodiment, the specified address of the memory unit MU The read data outputted from the random access memory is taken into the output launch OL when its level is established, and is held until the next read data of the random access memory to be activated is established.

Therefore, as shown in FIG.
~Ai is counted up and a series of addresses Ab-Ab
When ÷3 is specified sequentially, the recovery time tRC of the random access memory to be activated first and the access time tAc of the random access memory to be activated next are within the cycle time tcZ of the memory unit MU. 'lA is collected. As a result, the cycle time tc2 of the memory unit MU is approximately equal to the data retention time t
The time is reduced to the time equivalent to OH.

On the other hand, as shown in FIG.
I is assumed to be address Ab, which happens to be 4 addresses added to address Aa, and is, for example, random access memory RA.
When M0 is activated twice in a row, it is necessary to precharge the complementary data line during this period, and the recovery time tR is required.
Therefore, the cycle time tel of the memory unit MU becomes tC1'l tOH+tRc, which is longer than the cycle time tel when the address signals AO to Ai are counted up. I have no choice.

Here, the number of random access memories provided in the memory unit MU is n, and the address signals AO to At
If the probability that the random access memory is generated randomly without being counted up is 1/p, the probability P that the same random access memory will be in the operating state twice in a row is P= (1/n) x (1/p ) -1/(nXp). Therefore, by applying the present invention, the average cycle time tc of the memory unit MU is also shortened to approximately its data retention time tOH, and its output throughput is equivalently improved.

As described above, the memory unit MU of this embodiment has a basic configuration of four random access memories RAMOA-RAM3 to which a series of addresses are sequentially assigned. These random access memories are selectively activated in accordance with chip selection signals C8O to C33, which are selectively formed based on chip address signals csQ and csl, that is, address signals AO and A1 of the lower two bits. Ru.

The memory unit MU of this embodiment further receives internal output signals doO to do3 and timing signals φoeQ to φOe3 outputted from each random access memory when the random access memories RAM0 to RAM3 are activated in the read mode. Contains output buffer DOB.

The data output buffer DOB receives the above-mentioned timing signal φo.
The corresponding internal output signal do according to sQ~φoe3
an output selection circuit SEL that selectively transmits o to do3;
An output launch OL that is selectively brought into a cent state or a reset state according to an inverted set signal and an inverted reset signal T output from an output selection circuit SEL, and an output launch OL.
and an output drive circuit OD which sends out an output signal of through the data output terminal Dout, so that the read data output from each random access memory is next activated after its level is established. Data output buffer D until read data of random access memory is established.

It is held in the output latch OL of B and sent out. Therefore, the cycle time of the memory unit MUO in this embodiment is reduced to approximately the data retention time LDH, and the output throughput of the memory unit MU is isometrically improved.

As shown in the above-described embodiment, when the present invention is applied to a memory unit or the like that includes a plurality of random access memories and employs an interleaving method, the following effects can be obtained. That is, (1) the read data of each random access memory, etc. is transferred to a memory unit, etc., including a plurality of random access memories, etc., which are alternatively put into an operating state according to a corresponding activation selection signal, and which are then put into an operating state. By providing an output circuit that retains the read data of the random access memory until it is established and sends it to the outside, an effect can be obtained in that it is possible to prevent output contention among multiple random access memories that constitute a memory unit, etc. It will be done.

(2) According to the above item (11), it is possible to obtain the effect that the cycle time of the memory unit etc. can be shortened to a time corresponding to a predetermined data retention time.

(3) Items (1) and (2) above provide the effect that the output throughput of a memory unit, etc. that includes a plurality of random access memories and adopts an interleaving method can be increased.

(4) Items +1) to (3) above provide the effect that the processing capacity of a digital processing device or the like including the memory unit can be increased.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, in FIG. 1, when the internal output signals doQ to do3 are gate-controlled in accordance with the output control signals in the random access memories RAM0 to RAMa, the timing signals φoeo to φoe3
can be replaced, for example, with inverted signals of the chip selection signals C8O to C33, respectively. Also, output MO5F
ETQI and Q2 may be driven after gate-controlling the output signal of the output latch OL, that is, the internal signal Od and the inverted internal signal od, by a common output control signal. At this time, the output drive circuit OD functions as a tri-state output circuit. In FIG. 2, memory unit MU
may be provided with any number of random access memories. Furthermore, the memory unit MU may be provided with a function of outputting the timing signals φoeQ to φos3 or their logical sum signal. Furthermore, various implementations such as the specific circuit configuration of the data output buffer DOB shown in FIG. 1, the block configuration of the memory module (MU) shown in FIG. 2, and the combination of control signals and address signals shown in FIG. It can take any form.

In the above explanation, the invention made by the present inventor will be mainly described in the multiple 81/CMO fields that are the background of the invention.
Although we have explained the case where it is applicable to a memory unit consisting of S dynamic type RAM, it is not limited thereto. The present invention is widely applicable to semiconductor memory devices that include at least a plurality of memory circuits and employ an interleaving method, and to digital devices that incorporate such semiconductor memory devices.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, data read from each random access memory is transferred to a memory unit, etc., which includes a plurality of random access memories, etc., which are selectively put into an operating state according to a corresponding activation selection signal, and a random access memory, etc., which is then put into an operating state. By providing an output circuit that holds the read data until it is established and sends it to the outside, it is possible to prevent output contention between multiple random access memories and the like.

This makes it possible to shorten the cycle time of a memory unit, etc. that includes a plurality of random access memories and employs an interleaving method, and to increase its output throughput.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a data output buffer (output circuit) of a memory unit to which the present invention is applied, and FIG. 2 is an embodiment of the memory unit including the data output buffer of FIG. 1. FIG. 3 is a timing diagram showing an example of the read operation of the memory unit shown in FIG. 82. FIG. 4 is a timing diagram showing an example of the read operation of the conventional memory unit having an incremental function. It is. MU...Memory unit, DOB...Data output cover sofa, SEL...Output selection circuit, OL...Output nozzle, OD...Output drive circuit, 01-G12...
Nant gate circuit, N1 to N6...inverter circuit,
Q1~Q2...N channel MO3FET. C3L...Chip selection circuit, RAM0~RAM3...
・Random access memory.

Claims (1)

[Scope of Claims] 1. A plurality of memory circuits that are selectively put into an operating state in accordance with a corresponding activation selection signal and read out stored data at a designated address; and an output circuit that holds the read data of the memory circuit until it is established and sends it to the outside. 2. The output circuit includes an output selection circuit that selectively transmits read data of the corresponding storage circuit according to the output control signal or the activation selection signal, and a set state or reset selectively according to the output signal of the output selection circuit. 2. The semiconductor memory device according to claim 1, further comprising an output latch that is set to a state, and an output drive circuit that outputs an output signal of the output latch to the outside. 3. The semiconductor memory device according to claim 1 or 2, wherein each of the memory circuits is constituted by a Bi-CMOS dynamic RAM.