JPH0730435A - Error correcting circuit - Google Patents

Abstract

PURPOSE:To detect and correct an error generated in a frame converting memory at the time of converting digital data into a frame by means of simple constitution. CONSTITUTION:The phase of input data 10 is successively shifted by respective delay circuits 111, 112 and phase-shifted contents are written in memories 101 to 103 at the same timing. Data stored in the memories 101 to 103 are read out at the same timing add the phases of respective read data are corrected by respective delay circuits 113, 114 so as to coincide with each other. A majority value among data 20 to 22 having a coincident phase is determined by a majority circuit 121 and outputted as output data 31.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction circuit, and more particularly to an error correction circuit of a memory circuit for frame conversion in a digital transmission system.

[0002]

2. Description of the Related Art The structure of a frame converter for transmitting data in a digital transmission system is shown in FIG. The input data 10 to be transmitted is written to the frame conversion circuit (memory circuit) 101 in the memory control circuit 15 for writing.
Under the control of 1, the data is sequentially written at the timing 71 synchronized with the input data rate 61.

Reading data from the memory circuit 101 is
Under the control of the read memory control circuit 152, it is carried out in synchronization with the timing 72 of the read request signal 62, and is derived as frame-converted data 31.

Here, the data written in the memory circuit 101 is erroneously rewritten in the memory, or the memory circuit 1
In some cases, erroneous data may be output due to an error in the timing of the data write control signal or the read control signal for 01.

In this case, as means for knowing that the data is normally output, it is judged whether the number of bits of "1" is an even number or an odd number in the data of the input and the output of the frame conversion circuit 101. If not, there is a parity method that detects an error. FIG. 3 shows an example of using this parity method, in which the frame conversion circuit 101 composed of a memory has a parity circuit 13 for error detection.
1, 132 and the comparison circuit 141 are connected.

The input data signal 10 is a frame conversion circuit 1
01, and also to the parity circuit 131. The parity circuit 131 determines whether the "1" bit is an even number or an odd number in a certain section of the input signal, for example, in one frame. Frame conversion circuit 101
The output data signal 31 is input to the parity circuit 132, and the parity circuit 132 determines whether the number of “1” bits in the same section as the parity circuit 131 is an even number or an odd number.

The two parity circuits 131 and 132
The output signals 41 and 42 of are compared by the comparison circuit 141,
If they are the same, it is determined that there is no error, and if they are different, it is determined that there is an error, and the error determination signal 51 is output.

When this parity method is used, even if an even number of errors occur, the parity circuits 131 and 132 respectively judge whether the number of "1" bits is an even number or an odd number. The error cannot be detected. Therefore, a method in which the parity circuit is arranged in three columns and an even number of errors are detected as in Japanese Patent Laid-Open No. 03-049321 can be considered.

[0009]

In such a conventional frame conversion error detection circuit using parity, an error is detected by determining whether the number of "1" bits in a specific section of the parity circuit is an even number or an odd number. Therefore, there is a drawback that the error cannot be corrected because the bit itself in which the error occurred within the specific section cannot be specified.

Further, there is a drawback that the memory control circuit causes an error even if the timing of writing or reading to the memory is momentarily erroneous due to noise or the like.

It is an object of the present invention to provide an error correction circuit which can easily detect and correct an error occurring in a frame conversion memory circuit at the time of converting a frame of digital data without using a parity method. Is.

[0012]

An error correction circuit according to the present invention comprises means for sequentially shifting the phase of input data and outputting three or more pieces of phase shift data, and each of these phase shift data at the same write timing. Memory means for writing and reading at the same read timing respectively, means for phase-matching each read data of this memory means, and a majority decision of the values of each data after this phase-matching to determine the majority decision value as output data. And a majority decision means that

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.
The same parts as those in FIG. 3 are denoted by the same reference numerals. In the embodiment of FIG. 1, three frame conversion circuits 101, 10 of the same type are used.
2, 103, and delay circuits 111, 112, 11 for delaying the input and output of each frame conversion circuit.
3, 114 and the delay-corrected frame conversion circuit 101
10 to 103, and a majority decision circuit 121 for majority decision of the output signals 20 to 22.

Next, the operation of this embodiment will be described with reference to the time chart of FIG. The input signal 10 is the write memory control circuit 151 and the read memory control circuit 152.
To the three frame conversion circuits 101 to 103 whose writing and reading of the memory are controlled by the delay circuit 11
1 and 112 have different delays (phase difference) depending on the delay circuit
Entered in.

Therefore, each frame conversion circuit outputs a converted signal that has undergone frame conversion. Since the output signals have different phases, the delay circuit 11 is provided.
This is corrected by 3, 114, and three frame conversion outputs 20, 21, 22 having the same delay amount (phase matched) are generated and input to the majority circuit 121. Majority circuit 1
In 21, it is determined which of the three input signals 20 to 22 is “0” or “1” for each bit, and the larger one is output as the transmission frame conversion output 31.

Here, as one of the factors causing the error in the frame conversion circuit, malfunction of the control circuit controlling the memory is considered. In this case, the three frame conversion circuits simultaneously cause an error.

Therefore, in this embodiment, the input signal 10 is input to the three frame conversion circuits while sequentially shifting the phases by the delay circuits 111 and 112. Figure 2 (A)
Then, each column is shown as an example when it is delayed by one bit.

At this time, the three frame conversion circuits are simultaneously damaged during the address processing of the shaded area in FIG. 2A, but at the same address of the three frame conversion circuits,
Since different data are processed respectively, at the input of the majority circuit 121 after the phase of the data has been corrected, the erroneous bits are dispersed as shown in FIG.
The data not damaged by 21 is selected.

As a result, the probability that bits of two or more frame conversion circuits will be erroneous at the same time is extremely small, and frame conversion can be performed with almost no error.

Although the input data is branched into three in the above, it is obvious that the input data may be branched into five.

[0022]

As described above, according to the present invention, 3
Since the frame conversion circuit and the majority decision circuit are provided, the error can be directly corrected by selecting three or more output signals by the majority decision circuit. Further, according to the present invention, the delay circuits are provided with different delays for three or more frame conversions, so that even if there is a malfunction of the memory control circuit that causes an error in three or more frame conversion circuits at the same time, the error can be corrected. There is also the effect that it can be done.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

2 shows the operation of the block of FIG. 1, (A) shows the data phase relationship of each input side of the frame conversion circuit,
(B) is a time chart showing a data phase relationship on each output side of the frame conversion circuit.

FIG. 3 is a block diagram showing an error detection method of a conventional frame conversion circuit.

[Explanation of symbols]

 10 Input data 11, 12 Phase shift input data 20-22 Output data after phase matching 31 Frame conversion data 71 Write timing signal 72 Read timing signal 101-103 Frame conversion circuit 111-114 Delay circuit 121 Majority decision circuit 151 Write memory control Circuit 152 Read-out memory control circuit

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[Procedure amendment]

[Submission date] January 10, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

Claims (1)

[Claims] 1. The phase of input data is sequentially shifted to 3
Means for outputting more than one phase shift data, memory means for writing each phase shift data at the same write timing and reading at the same read timing, and means for matching the phase of each read data of this memory means ,
An error correction circuit comprising a majority decision means for judging the majority decision of the value of each data after the phase adjustment and using the value of the majority decision as output data.