JPH02144745A - Memory card - Google Patents

Abstract

PURPOSE:To keep an input signal at a constant level to a memory by securing the logic between the input signal received from an input terminal and the output of a latch circuit which is backed up by a battery. CONSTITUTION:One of both inputs of an AND circuit l3 is changed to H from L and the other input is changed to L after it is kept at H for a fixed time by a delay circuit D3. Thus a contact N1 is turned to L after the output of H having a fixed width. Meanwhile a counter N2 is kept at H. As a result, an FFl2 latches the H of a D terminal and the output Q is set at H and the output phia of an OR circuit l1 is set at H. Under such conditions, the signal phia is always kept at H and the data on a memory is held. When a memory card is removed, a terminal VCC and the signal phi1 are set at L. However the output Q is kept at H since the FFl2 is backed up by a power supply VBB. Thus the output phia of the circuit l1 is kept at H and the memory data can be held.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a portable memory card containing volatile memory and a battery, and in particular to data retention characteristics.

[Prior Art] Conventionally, this type of technology has involved connecting the input signal line of a memory card to the ground level via a resistor.

One of the conventional examples will be explained using FIGS. 5 and 6. In Figure 5, the memory card terminal ■CC is a diode di
The cathode of d15 connected to the anode of 5 is VB
B is connected to a built-in memory IC (not shown), and is also connected to the anode of a built-in battery (not shown) to hold the data content of the memory IC by the battery. The card input signal φ1 is input to the 3-state buffer TBI. The card input signal φ3 is input to the output control terminal of the 3-state buffer TB1, and when φ3 is at a low level, the output φa5 of the 3-state buffer becomes high impedance.

Further, when φ3 is at a high level, data of φl is output to φa5. The power supply of this 3-state buffer 77B1 is VB
Connected to B. The signal φ1 is connected to ■C via the resistor R51.
Connected to C. A resistor R52 connects the power supply CC and GND. Signal φ3 is connected to GND via resistor R53. Signal φa5 is connected to VBB via resistor R54.
is connected to.

Next, the operation of this conventional example will be explained using FIG. First, when the signal φa5 for the memory is at a high level, the memory is in a data holding state, and when it is at a low level, it is in an operation mode such as writing, and the retention of data in the memory is not guaranteed. For example, if the memory is composed of a static RAM, the control signal may be a chip select terminal TE or a write enable signal W.

Further, NO shown in FIG. 6 indicates a noise pulse generated at the terminal of the memory card. To be more specific, FIG. 6 shows v
It shows the change in the signal at the time of transition between data retention when CC is supplied from the outside and data retention by the built-in battery. In the state where vCC is supplied, the signal φ1
Also, the signal φ3 is at high level, so that the signal φ
a5 becomes high level. Thereafter, even if the signal φ3 is set to a low level and the output of the 3-state buffer TBI is set to high impedance, the output of the signal φa5 is maintained at a high level by the resistor R54. Therefore, when CC is supplied, φ3 is at a low level and the signal φa5 is at a high level. Next, when the card is removed from the device and carried around, VCC is not supplied, and the state is backed up by the built-in battery, the signal φ1 is transferred to the resistor R51 and the resistor R52.
It is connected to GND and becomes a low level.

At this time as well, the signal φ3 is connected to GND by the resistor R53 and is held at a low level. This causes the signal φa5
The output of the 3-state buffer output TBI is high impedance, and is maintained at a high level by the resistor R54. In addition, since the signal φ3 can be maintained at a low level during the transition from battery backup to operation using vCC supply, the output of the signal φa5 is maintained at a high level, and the data in the memory is retained without being changed. .

[Problems to be Solved by the Invention] In the conventional example described above, the signal φ1 is at a low level when memory data is held in the built-in battery, and the signal φa5 is kept at a high level by the low level of the signal φ3 and the resistor R54. Guaranteed.

On the other hand, the resistor R54 depends on the low level output standard of the 3-state buffer TBI in order to satisfy the low level of φa5 during memory operation, and since it is impossible to reduce the resistance value beyond a certain value, the signal φa5 suddenly It cannot respond to level 1 Hi. Furthermore, for the same reason, it is impossible to reduce the resistance value of the resistor R53 below a certain value in order to satisfy the high level of the signal φ3. For such a card, NO is applied to the input terminal of signal φ3 when data is held by the battery.
If noise such as static electricity occurs,
Since the signal φ1 is at a low level, the output of the 3-state buffer is turned on and instantly becomes a low level, resulting in the destruction of data in the memory.

[Differences between the invention and the prior art] In contrast to the above-mentioned conventional memory cards, the present invention manually outputs a logic output to a built-in memory with a signal whose output is held by a built-in battery for one input word line of the memory card. have differences.

[Means for Solving the Problems] The memory card of the present invention includes a latch circuit whose output can be held by a built-in battery, inputs an input signal and the output of the latch circuit, and stores the logic output in the memory. and a circuit for distinguishing between the data holding state and the memory card operating state and controlling the output of the latch circuit.

[Example code] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

vCC is the TL source terminal of the memory card, and is connected to the anode of the diode dil. Diode (I
The cathode of i1 is connected to the internal power supply VBB of the memory card. The internal power supply VBB is a power supply backed up by a built-in battery (not shown), and the memory IC
(not shown). Input signal φ1 is an OR circuit! 21 people are employed. The D-type flip-flop 92 has a D input terminal connected to VBB, and a CLK input terminal connected to a contact N1. The reset terminal π is connected to the contact N2. The output Q is input to an OR circuit 91. The output of the OR circuit 91 becomes φa and becomes a control line for the memory. Here, it is assumed that the memory can hold memory data when the signal φa is at a high level, and data retention is not guaranteed when the signal φa is at a low level. Input signal φ2 is connected to resistor R5. The other end of the resistor R5 is connected to the base of the NPN transistor Tri.

One end of the resistor R6 is connected to the base of the transistor Tri. The other end of the resistor R6 is connected to the emitter of the transistor Tr1 and also to GND. The collector of transistor Tri is connected to contact N3. The logic circuit father 3 receives an inverted signal from the delay circuit D3. Further, the signal at the contact N3 is connected to the other input of the AND circuit 93. The output of the OR circuit 94 is connected to the contact N2. The inverted signal at contact N4 is connected to the input of OR circuit 94. The output of the OR circuit 9!5 is connected to the input of the OR circuit 94. One end of the delay circuit D1 is connected to the contact N3. The other side is connected to the input and delay port ff12 of the OR circuit 95. The other end of the delay circuit D2 inverts the signal and inputs it to the OR circuit 95.

One end of the resistor R1 is connected to VBB, and the other end is connected to the contact N3. One end of the resistor R2 is connected to the power supply CC, and the other end is connected to the contact N4. One end of the resistor R3 is connected to the power supply CC, and the other end is connected to the signal φ1. One end of the resistor R4 is connected to the power supply CC, and the other end is connected to GND. Here, the logical sum circuit 9
1. flip flop92. AND circuit 93. OR circuit 94. OR circuit S! The power supply of No. 5 is connected to VBB to enable battery backup.

How to insert/remove a memory card using Figure 2? ! The operation of this embodiment as the source changes will be explained. First of all ■
During memory card operation on CCCC supply, input signal φ2
is at a high level, and the potential of the base of the transistor Tri is determined by the resistors R5 and R6. At this time, the values of the resistor R5 and the resistor R6 are determined so that the transistor Tri is turned on in response to the high level voltage of the input signal φ2. As a result, contact N3 is at a low level. Contact N4 is at a high level because it is connected to vCC via resistor R2. Due to these human forces, the node N1 is at a low level and the contact point N2 is at a high level. It is also assumed that the output of the flip-flop 92 is at a low level. As a result, the input signal φ1 is transmitted to φa and serves as a memory control signal. Subsequently, the signal φ2 is set to a low level when power is supplied. This turns off the transistor Tri. As a result, the contact N3 changes from a low level to a high level due to the resistor R1. As a result, one side of the AND circuit 9.3's power changes from a low level to a high level. The other human power is maintained at a high level for a certain period of time by the delay circuit D3, and then changes to a low level. As a result, the two inputs are at a high level for a certain period of time, and the contact N1 becomes a low level after a high level with a certain width is output. On the other hand, contact N2 is maintained at a high level. This causes flip-flop 9
2 latches the high level of the D terminal, and the output Q becomes high level. As a result, the output of the OR circuit 91, ie, φa becomes high level. In this state, the signal φa is always at a high level, and the data in the memory is also held. In this state, insert/remove the card. First, when removing the memory card, the CC terminal and the signal φ1 are brought to a low level by the resistors R3 and R4. However, since the flip-flop 92 is backed up by the voltage gVBB, the output Q remains at a high level. This makes it a logical sum circuit!
The output φ0 of 21 is maintained at a high level so that memory data can be held.

At this time, the node N4 is at a low level due to the resistors R2 and R4, and the output of the OR circuit 94 which receives the inverted signal of the node N4 outputs a high level, so that the high level of the node N2 is maintained. Further, since the node N3 is at a high level due to the resistor R1, one of the inputs of the OR circuit 95 is at a high level, and the output of the OR circuit 95 is also at a high level, so that the OR circuit 9.4
Both inputs are at high level.

Subsequently, when the card is inserted into the device, the power supply VCC rises to a high level. The signal φ1 is set to a high level manually. Further, the signal φ2 is inputted at a low level. These are easy to define on the device side. When VCC becomes high level, the node N4 becomes high level, and the input of the OR circuit 24 which inputs the inverted signal of the node N4 becomes low level. When the input signal φ2 is set to a high level to perform a memory operation, the transistor Tri is turned on and the node N3 becomes low level. As a result, after a certain period of time due to the delay circuit D1, the human power of the OR circuit 95 is 2.
Both are at a low level, and the OR circuit 25 outputs a low level. Further, after a certain period of time by the delay circuit D2, one of the input signals becomes high level, and the output of the OR circuit father 5 becomes high level again. As a result, the output of the OR circuit 95 outputs a negative pulse. Logical sum circuit! 24, the signal at the node N4 first becomes low level due to the delay circuit D1. Afterwards, the output of the OR circuit 25 becomes low level for a certain period of time, and a low level pulse is given to the output node N2 during that period. Also, a logical OR circuit regarding this change in node N3! The output of 23 remains at a low level. This allows you to flip flop! The data of 22 is reset, its output Q becomes low level, and the external terminal signal φl becomes φ
The data is transmitted to a to enable control of the operation of the memory.

In this embodiment, by controlling the signal φ2, it is possible to control the data in the flip-flop 92 and maintain the signal for holding memory data regardless of the input from the external terminal.

Further, since the reset signal control is performed for the data of the flip-flop using both the power supply and the input signal, it is effective in retaining memory data even against noise from external terminals.

FIG. 3 is a diagram for explaining a second embodiment of the present invention.

Here, ICI is a power supply monitoring IC, and is an IC that generates a signal in response to voltage fluctuations in the power supply VCC. In this embodiment, the power supply terminal is connected to the card input power supply terminal CC, and the GND terminal is connected to the card GND. The signal output terminal is connected to node N33. Card power supply terminal ■CC is connected to internal voltage #VB via diode di3
Connected to B. OR circuit 931 receives input signal φ1
The output Q of the foot flop 932 is inputted to become the memory control signal φa3. The input terminal of the flip-flop 932 is connected to VBB, the CLK terminal CLK is connected to the node N31, and the reset terminal π is connected to the node N32. Logical sum circuit! 234 is connected to VCC by resistor R31
Inversion of node N34 connected to (word and OR circuit 935
The output is done manually.

Resistor R32 is connected between φ1 and VCC. Resistor R3
3 is connected between VCC and GND.

These are the same as in the first embodiment. The AND circuit 933 inputs the inverted signal of the node N33 and the signal delayed by the delay circuit D3, and its output is connected to the node N31. The OR circuit 9.35 inputs the inverted signal of the signal delayed by the delay circuit D1 of the node N33 and the signal of the node N33 delayed by the delay circuits D1 and D2, and outputs the OR circuit! It is connected to 235 human power sources. Also logic circuit 931~!
235 is backed up by a battery.

The operation of this embodiment will be explained using FIG. When power is supplied: - When CC is at a high level, the input signal φ1 is at a high level, and the memory is in a data retention state. When VCC decreases by removing the memory card from the device, the voltage at node N33 shifts from high level to low level when the voltage falls below a certain value due to ICI. As a result, the output N31 of the AND circuit 933 outputs a high level, and then becomes a low level after the time of the delay circuit D3. As a result, the flip-flop 9.32 latches the high level of the D terminal, sets the output Q to a high level, and sets φa3 to a high level. This allows the memory to retain data. Subsequently, when a memory card is inserted into the device, VCC increases. Along with this, the level of node N33 rises due to ICI and shifts from a low level to a high level. Further, the node N34 transitions from a low level to a high level due to the resistor R31. As a result, the human power on one side of the OR circuit 934 becomes low level. However, because of the delay circuit D1, the OR circuit 9
No. 35 input does not change for a certain period of time.

It is easy to make this delay time longer than the time when node N34 becomes high level. As a result, the OR circuit 934
OR circuit before the inverted signal input of node N34 becomes low level! 235 output change is prohibited. Then node N
33 becomes high level and after the delay time by the delay circuit D1,
Both inputs of the OR circuit 935 become low level, and the output becomes low level. After the delay time of the delay circuit D2, the output becomes high level and remains high level thereafter. This causes the output of OR circuit 934 to generate a low level pulse. Therefore, a low level pulse is input to the π terminal of the flip-flop 932, and the output Q becomes a low level. As a result, one of the inputs of the OR circuit becomes low level, the signal of the input signal φ1 is transmitted to φa3, and the memory can be controlled and operated.

In this embodiment, the memory system 1jl inside the memory card is
The l signal φa3 can be easily maintained at a high level by using a flip-flop. Furthermore, since the voltage detection IC is used to control the data of the flip-flop, there is no need to control input signals.

[Effects of the Invention] As explained above, the present invention provides a memory card with a built-in battery for data retention, in which the input signal from the input terminal is logically connected to the output of the latch circuit backed up by the battery. The input signal level can be held constant, making it easy to retain memory data backed up by batteries, and the effect is that it can provide a memory card that has sufficient resistance to noise during the backup period. be.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation of the first embodiment of the present invention, and FIG.
The figure is a circuit diagram showing a second embodiment of the present invention, FIG. 4 is a waveform diagram used to explain the second embodiment of the present invention, FIG. 5 is a circuit diagram showing a conventional example, and FIG. FIG. 3 is a waveform diagram used to explain a conventional example. i5 R1~R6・・・・・・・・・・・・9.1
．． ! 24. 95 ・ ・ ・ ・ ・ 92
・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・93
・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・D
1~D3 ・ ・ ・ ・ ・ ・ ・ ・Tr
i ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・
Resistors, OR circuits, flip-flops, AND circuits, delay circuits, transistors. Figure 5

Claims (1)

[Claims] A latch circuit backed up by the built-in battery for the input signal line of the card in a portable memory card that has volatile memory and a built-in battery to retain data written in the memory when the power is turned off or when the card is carried. A memory card characterized in that an input signal to the memory is held constant by performing logic with an output signal of the memory card.