JPH0214493A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce only a threshold value of a memory cell without lowering the power voltage by using a voltage reduction means so as to lower the voltage applied to each memory cell than the power voltage. CONSTITUTION:A word line driver 20 consists of a P-channel MOS transistor (TR) 11 and an N-channel MOS TR 12, and the word line 3 is connected to each drain of the P-channel MOS TR 11 and the N-channel MOS TR 12. Then an N-channel MOS TR 7 is inserted between a source of the P-channel MOS TR of the word line driver 20 and power supply, the N-channel MOS TR 7 constitutes the voltage reduction means to reduce the voltage from the power supply and to apply the resulting voltage to the memory cell. Thus, the voltage lower than the power voltage is used, the threshold value of the memory cell is set lower accordingly.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention mainly relates to a semiconductor memory device including a channel cut type ROM, and more specifically, memory cells are arranged in a plurality of rows and columns. The threshold value of the memory cell is set to the first size or the second size depending on the address consisting of the column.
The present invention relates to a semiconductor memory device that stores data by selecting and setting the size in advance.

[Prior Art] A commonly known semiconductor memory device of this type is one shown in FIG. 6, for example.

FIG. 6 is an overall diagram of a semiconductor memory device including a 1 bit x 16 word ROM. In the figure, reference numeral 1 denotes a memory cell array consisting of a plurality of memory cells 5 arranged in a plurality of rows (four rows in the drawing) and plural columns (four columns in the drawing).

Reference numeral 22 denotes an X decoder, which is an example of row selection means, and supplies eight high level signals or low level signals to each word line driver 20 based on address input signals Aφ and Al. When a high level signal is input to the word line driver 20, a low level signal is output to the word line 3 connected to the word line driver 20. In other words, the word line driver 20 is
It is constituted by an inverter consisting of an N-channel MOS (MOS) transistor and a P-channel MO (MOS) transistor, and a voltage is applied by a power supply 26, and is configured to output human power in an inverted state. Further, the X decoder 22 is composed of an inverter 30 and a NAND circuit 34 consisting of a P-channel MOS transistor and an N-channel MOS transistor, and has four NAND circuits.
A low level signal is output from one of the D circuits 34, and a high level signal is output from the other three. and,
The NAND circuit 34 outputting a low level signal is appropriately selected by four types of combinations of low level and high level signals of the address input signals Aφ and AI. Then, only the word line 3 connected to the word line driver 20 into which the low level signal output from the NAND circuit 34 is input becomes a high level state, and the memory cell 5 existing in the row belonging to that word line 3 is set to a high level. The signal will be input as a gate signal.

In other words, the memory cell 5 is composed of an N-channel MOS transistor, and a high-level signal is input to the gate electrode of the N-channel MOS transistor. When the threshold value is lower than the input gate voltage, the N-channel MOS transistor becomes conductive,
If the threshold is higher than the gate voltage, N channel M
The OS transistor does not become conductive. Data is stored depending on the threshold value of each memory cell.

In the figure, 24 is an X decoder which is an example of column selection means, and is composed of an inverter 32 and a NOR circuit 36, and only one of the plurality of NOR circuits 36 outputs a high level signal. Other NOR circuit 36
A low level signal is output from. The NOR circuit 36 outputting a high level signal can be appropriately selected by combinations of four types of high level and low level signals in the address input signals A2 and A3. The output from the NOR circuit 36 is input to the gate of an N-channel MOS transistor 38 provided on the bit line 4. Then, the N-channel MOS transistor 38 to which the high-level signal is input becomes conductive, and the N-channel MOS transistor 38 to which the low-level signal is input
Channel MOS transistor 38 is in a non-conductive state.

As described above, the X decoder 22 can select a row of memory cells 5 consisting of multiple rows and multiple columns.
The X decoder 24 makes it possible to select a column of memory cells 5 consisting of multiple rows and columns, and to select and specify one memory cell 5 existing in the selected row and column. . Then, a voltage from the power supply 26 is applied to the selected and specified one memory cell 5, and the N-channel MOS of that memory cell is
Depending on whether the threshold value of the N-channel MOS) transistor is high or low, it is determined whether the N-channel MOS) transistor is in a conductive state or not, as described above, and whether or not the N-channel MOS transistor is in a conductive state is determined by the sense, which is an example of a state determining means. It is configured so that it can be detected by an amplifier 28. Note that the voltage VDO from the power supply 26 is applied to each inverter 30 of the X decoder 22 and the NAND circuit 34 in addition to the word line driver 20.
is also supplied to the inverter 32 of the X decoder 24.
It is also supplied to the NOR circuit 36 and the sense amplifier 28.

[Problems to be Solved by the Invention] In this type of conventional semiconductor memory device, the word line 3 selected by the It is necessary to set the threshold value of the memory cell 5 having a high threshold value higher than the rising voltage of the word line 3. However, in order to obtain such a high threshold, it is necessary to implant high-concentration impurities at the manufacturing stage of the memory cell 5, which poses difficulties in the wafer process and also reduces the electrical withstand voltage of the transistor in the memory cell. This has the drawback of resulting in a semiconductor memory device with low reliability. Therefore, it is conceivable to set the voltage VOD of the power supply 26 to a low value from the beginning, but as mentioned above, the voltage from the power supply 26 is applied to the X decoder 22 and the Y decoder 24 in addition to the word line driver 20. This voltage is also applied to various other circuits such as VDD, and a new drawback arises in that by lowering the voltage VDD of the power supply 26, various inconveniences occur in the various other circuits.

SUMMARY OF THE INVENTION In view of the above circumstances, it is an object of the present invention to provide a semiconductor memory device in which only the threshold value of a memory cell can be lowered without lowering the power supply voltage.

[Means for Solving the Problems] A semiconductor memory device according to the present invention includes a memory cell that changes between a first logic state and a second logic state depending on the magnitude relationship between an applied voltage and a predetermined threshold value. includes a memory cell array arranged in a plurality of rows and columns, a row selection means for selecting each row of the plurality of memory cells, and a column selection means for selecting each column of the plurality of memory cells. means, a power source for applying a voltage to a predetermined device, and voltage reducing means for reducing a voltage from the power source and applying it to the memory cells, the plurality of memory cells are configured to said first in response to a voltage applied by said means.
a first memory cell whose threshold value is set to be in a logic state; and a first memory cell whose threshold value is set to be in a logic state of a set second memory cell, wherein the memory cell selected by the row selection means and the column selection means is set to the first logic state or the second logic state in response to the applied voltage. The present invention is characterized in that it further includes state determining means for determining which of the logical states it is in.

[Operation] The memory cell array includes a plurality of memory cells arranged in a plurality of rows and a plurality of columns, and the memory cells have a first logic state and a first logic state depending on the magnitude relationship between the applied voltage and a predetermined threshold. 2 logical states. Further, each row of the plurality of memory cells is selected by the row selection means, each column of the plurality of memory cells is selected by the column selection means, and a predetermined memory cell is selected and specified by both selection means. . Further, the voltage from the power source is applied to the memory cell in a reduced state by the voltage reducing means. Furthermore, the plurality of memory cells include a first memory cell and a second memory cell, and the first memory cell is set to a first logic state by the voltage applied by the voltage reduction means. The threshold value is set such that the second memory cell is brought into a second logic state by the voltage applied by the voltage reduction means. be. Then, by the action of the state determining means, the memory cell selected by the row selecting means and the column selecting means changes to the first logic state or the second logic state in response to the applied voltage. It is determined which state it is in.

In other words, memory cells are divided into a group of memory cells located at a predetermined address among a plurality of addresses consisting of rows and columns, and a group of other memory cells, and one group of memory cells is designated as a first memory cell. Data is stored by configuring the other memory cell group as a second memory cell, and the voltage applied to the memory cell selected by the row selection means and the column selection means The memory cell located at the predetermined address is determined to be the first memory cell or the second memory cell by determining whether the memory cell is in the first logic state or the second logic state in response to The stored data can be read out.

Since the voltage applied to each memory cell is lower than the voltage due to the voltage reduction means, the memory size is set based on the height of the applied voltage. The cell threshold can also be set correspondingly low.

[Embodiments of the invention] Next, embodiments of the present invention will be described based on the drawings.

FIG. 1 is a circuit diagram of a word line drive portion in a semiconductor memory device according to the present invention. In the figure, a word line driver 20 is composed of a P channel MOS transistor 11 and an N channel MOS transistor 12. 3 is a word line, and the P channel MOS
Transistor 11 and N-channel MOS transistor 12
are connected to their respective drain electrodes. 4 is a bit line, as shown in FIG.
It is connected to the sense amplifier 28 via an S transistor 38. 7 is an N-channel MOS transistor, and the gate electrode and drain electrode of this N-channel MOS transistor 7 are connected to each other, and a terminal connected to the connection part is connected to a power source 26 shown in FIG. Power supply voltage VDO is applied. And this N channel MOS)
A source electrode 8 of the transistor 8 is connected to a source electrode of a P-channel MO transistor 11. Further, the gate electrodes of the P-channel MOS transistor 11 and the N-channel MOS transistor 12 are connected to each other and connected to a terminal 6, and as shown in FIG. be done. Furthermore, the source of the N-channel MOS) transistor 12 is G
Connected to ND. In the figure, 5 is a memory cell,
It is composed of an N-channel MOS transistor, and the source of the N-channel MOS transistor is connected to GND.
The gate electrode is connected to the word line 3, and the drain electrode is connected to the bit line 4. Also,
There are two types of threshold values of the N-channel MOS transistors constituting the memory cell 5: a normal low value and a slightly higher threshold.

Next, the operation will be explained.

A signal obtained by decoding the address signal from the X decoder 22 (see FIG. 6) is input to the terminal 6, and when the decoded signal is at a low level, the P channel MOS transistor 11 and the N channel MOS transistor Although the output of the inverter 12 becomes a high level state, the potential of the high level output does not rise above the potential of the source electrode 8. On the other hand, N-channel MO
Since the gate electrode of the S transistor 7 is connected to the power supply 26 (see FIG. 6) together with the drain electrode, the potential of the source electrode 8 is changed from the power supply voltage VDO to the N channel MOS.
) Ranjstaf threshold voltage ■th (hereinafter referred to as Vthy
), the N-channel MOS
Transistor 7 is turned on, and the potential of source electrode 8 rises. As a result, the potential of the source electrode 8 is vo. -Vtht
biased towards. Therefore, word line 3 is charged to VDD-Vtb 7 when selected. Then, a predetermined number of N constituting the memory cell 5 connected to the word line 3 is
If the threshold of the channel MOS transistor is normal and low, the N-channel MOS transistor is turned on,
On the other hand, if the threshold of the N-channel MOS) transistor in the memory cell 5 is high near VDO-Vtht, the N-channel MOS) transistor is not turned on and jf
The sense amplifier 28 shown in FIG. 16 makes it possible to determine whether or not the memory cell 5 maintained at a predetermined address is turned on.
data can be read. At this time, the word line does not rise to the power supply voltage V0° as in the conventional case;
Vth? Therefore, the threshold of the N-channel MOS transistor of the memory cell that does not turn ONL even when a voltage is applied does not need to be raised to around the power supply voltage VOD, but only needs to be raised to around Voo Vth7. That will happen. This N-channel MOS transistor 7 constitutes a voltage lowering means for lowering the voltage from the power supply and applying it to the memory cell.

Note that in the embodiment shown in FIG. A similar N-channel MOS) was inserted, but as shown in Figure 2, a similar
A plurality of channel MOS transistors 7 may be inserted in series.

In addition, as shown in FIG. 3, the sources of the P-channel MOS transistors of the word line driver 20 consisting of a plurality of inverters are connected to each other, and the common P-channel MOS transistors are connected to each other.
An N-channel MOS transistor 7 may be inserted between the source of the transistor and the power supply.

Furthermore, as shown in FIG. 4, the word line driver 20 is constructed of a P-channel MOS) transistor and an N-channel MOS) transistor instead of an inverter.
An ND circuit may be used, and as shown in FIG.
A NOR circuit including a P-channel MOS transistor and an N-channel MOS transistor may be used. In this case, signals from separate decoders may be input to the two input terminals 50a and 50b, or a signal from the decoder may be input to one input terminal 50a, and a clock signal may be input to the other input terminal. You may also enter Note that 7 in FIGS. 4 and 5 is an N-channel MOS transistor which is an example of voltage reducing means.

[Effects of the Invention] In the present invention having the above configuration, since the voltage applied to each memory cell is lower than the power supply voltage due to the action of the voltage reducing means, the height of the applied voltage can be reduced. The threshold value of the memory cell whose size is set as a standard can also be set lower accordingly, making it possible to lower only the threshold value of the memory cell without lowering the power supply voltage, making wafer processing easier. At the same time, it has become possible to provide a highly reliable semiconductor memory device due to improved electrical withstand voltage.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing essential parts of a semiconductor memory device according to the present invention. FIG. 2 is a circuit diagram of main parts showing another embodiment of the present invention. FIG. 3 is a circuit diagram of main parts showing still another embodiment of the present invention. FIG. 4 is a circuit diagram of a main part showing still another embodiment of the present invention. FIG. 5 is a circuit diagram of a main part showing still another embodiment of the present invention. FIG. 6 shows a conventional example and is an overall circuit diagram of a semiconductor memory device. In the figure, 5 is a memory cell, 1 is a memory cell array, 22 is an X decoder which is an example of row selection means, 24 is a Y decoder which is an example of column selection means, and 7 is an N channel MOS transistor which is an example of voltage reduction means. , 28 are sense amplifiers which are an example of state determining means.

Claims (1)

[Claims] A plurality of memory cells that change between a first logic state and a second logic state depending on the magnitude relationship between an applied voltage and a predetermined threshold are arranged in a plurality of rows and a plurality of columns. a memory cell array comprising: a row selection means for selecting each row of the plurality of memory cells; a column selection means for selecting each column of the plurality of memory cells; and for applying a voltage to a predetermined device. a power supply, and voltage reduction means for reducing a voltage from the power supply and applying it to the memory cells, and the plurality of memory cells are configured to reduce the voltage from the power supply in response to the voltage applied by the voltage reduction means. 1
a first memory cell whose threshold value is set to be in a logic state; and a first memory cell whose threshold value is set to be in a logic state of a set second memory cell, wherein the memory cell selected by the row selection means and the column selection means is set to the first logic state or the second logic state in response to the applied voltage. further comprising state determining means for determining which of the logical states the device is in;
Semiconductor storage device.