JPH02145014A - Pulsing circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a pulsing circuit that outputs a pulse corresponding to the peak point of an analog signal such as a read signal of a magnetic head.・An absolute value differentiating circuit that differentiates the absolute value of a human-powered analog signal; a zero-crossing detection circuit that detects the zero-crossing point of the output signal of the absolute value differentiating circuit; and a positive/negative level of the output signal of the absolute value differentiating circuit. A level slice circuit that slices at the slice level and a positive output signal of the level slice circuit.

a flip-flop that resets with a negative output signal; and a gate circuit that adds the output signal of the flip-flop and the output signal of the zero-cross detection circuit to output a pulse corresponding to the peak point of the input analog signal. It was configured with the following.

[Industrial application field]

The present invention relates to a pulsing circuit that outputs a pulse corresponding to a peak point of an analog signal such as a read signal of a magnetic head.

When detecting the peak point of an analog signal with a high bit rate and converting it into a pulse, the influence of level fluctuations and noise components of the analog signal increases, resulting in more errors. Therefore, it is desired to eliminate such influence.

[Conventional technology]

In data transmission systems and data processing systems including computers, there is a demand for faster processing as the amount of processing increases, and for example, magnetic disk devices as external storage devices are also required to have a larger capacity. Increasing the capacity of a magnetic disk device can be achieved by increasing the recording density, but in this case, the bit recording density, the trunk recording density, or both must be increased.

With this increase in recording density, errors occur more frequently when processing read signals from magnetic heads. For example, when the track recording density is increased, the track spacing becomes narrower, which tends to cause space talk in which a signal from an adjacent track is superimposed on a read signal from a target track, thereby degrading the error rate. Furthermore, if a positioning error of the magnetic head occurs for some reason and a signal from an adjacent track is superimposed on a read signal from the target trunk, the error rate also deteriorates. Furthermore, when the bit recording density is increased, the read signal level becomes relatively low and the influence of noise components increases.

A conventional pulsing circuit that processes a read signal in such a magnetic disk device as an input analog signal and outputs a pulse signal corresponding to the peak point of the input analog signal has the configuration shown in FIG. 5, for example. 21 is a differentiation circuit, 22 is a zero-cross detection circuit, 23 is a level slice circuit, and 24 is a gate circuit. Further, examples of signals A to E of each part are shown in FIG. 6 with the same reference numerals.

As shown in Figure 6 (A), the input analog signal ε is
When “1” is a signal with positive or negative polarity and “0” is an O level signal, the differential output signal B of the differentiating circuit 21 is as shown in (B).Then, the zero-crossing detection signal C of the zero-crossing detection circuit 22 is shown in (C), and during the period corresponding to “0” of the input analog signal A, there is a change in the differential output signal B due to a noise component (not shown), so the zero-cross detection signal C is in the form of a continuous pulse. will be output to .

Further, the level slice circuit 23 slices the input analog signal A at slice level 5LISL2 in (A). Therefore, the output signal of the level slice circuit 23 becomes as shown in (D), and when the gate circuit 24 takes the AND of the zero cross detection signal C and the output ε, the output signal as shown in (E) is obtained. A signal E is obtained. That is, the pulse signal E corresponding to the peak point of the input analog signal A can be output.

[Problem to be solved by the invention]

In the configuration of the conventional example described above, the zero cross detection signal C
contains a noise component unrelated to the peak point of the input analog signal A, so the level slice circuit 23 forms an output signal for the period including the peak point of the input analog signal A, thereby eliminating the peak point. A pulse signal E is obtained based on a zero-cross detection signal C indicating a signal.

However, when the input analog signal A is used as a read signal in the above-mentioned high-density magnetic disk device, the sixth
The signal of the adjacent trunk is superimposed on the waveform shown in (A) of the figure. It is known that this crosstalk component has many low frequency components on the frequency axis, and the differentiator circuit 2
The influence on the level slice circuit 23 is greater than that in the case where the high frequency band is emphasized by 1. For example, if the slice level is set to a low level, the output signal will contain crosstalk components, and an erroneous pulse signal E may be output.
In addition, if the slice level is set high, it may not be possible to obtain an output signal including the peak point due to fluctuations in the read signal level, and the slice level setting range becomes extremely narrow due to noise components such as wolf talk. was there.

An object of the present invention is to provide a pulsing circuit that is less affected by noise components.

[Means to solve the problem]

The pulsing circuit of the present invention performs level slicing based on the differential output signal of the absolute value of the input analog signal,
This will be explained with reference to FIG.

An absolute value differentiator circuit 1 that calculates the absolute value of an input analog signal and then differentiates it; a zero cross detection circuit 2 that detects the zero-crossing point of the output signal of the absolute value differentiator circuit 1; A level slice circuit 3 that slices the level at a predetermined slice level, a flip-flop 4 that is set by the positive output signal of this level slice circuit 3 and reset by the negative output signal, and the output of the Q terminal of this flip-flop 4. This circuit includes a gate circuit 5 which adds the signal and the output signal of the zero-cross detection circuit 2 and outputs a pulse corresponding to the peak point of the input analog signal.

[Effect]

The absolute value differentiator circuit 1 converts the positive and negative polarities of the input analog signal into, for example, positive polarity and differentiates them, similar to full-wave rectification, and produces a differentiated output signal with a period twice that of the input analog signal. The peak point of the signal corresponds to the same slope portion of the differential output signal waveform.

The zero cross detection circuit 2 detects the zero cross point of the differential output signal.As mentioned above, since the peak point of the input analog signal corresponds to the same slope portion of the differential output signal waveform, the zero cross point corresponding to the peak point is detected. Points can be detected accurately.

The level slice circuit 3 slices the positive and negative levels of the differential output signal at predetermined positive and negative slice levels, respectively. The positive side output signal from this level slice circuit 3 is applied to the set terminal S of the flip-flop 4, the negative side output signal is applied to the reset terminal R of the flip-flop 4, and the Q terminal output signal is applied to the gate circuit 5. It will be done.

The gate circuit 5 is composed of, for example, an AND circuit, and the zero-cross detection signal during the period when the Q terminal output signal of the flip-flop 4 is "1" becomes the output pulse signal.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention, showing a case where the read signal of the magnetic head 17 is an input analog signal. In the figure, 10 is an absolute value circuit, 11 is a differential circuit,
12 is a zero cross detection circuit 13 is a level slice circuit;
14 is a flip-flop, 15 is an AND circuit, and 16 is a preamplifier.

This is a pre-circuit that includes an equalization circuit, a filter, an automatic gain control amplifier, etc.

The read signal from the magnetic head 17 is subjected to amplification and 2-equalization processing by the pre-circuit 16, and is then applied to the absolute value circuit 10 as a manual analog signal a. This input analog signal a is converted from positive to negative polarity by an absolute value circuit 10, for example, and is applied to a differentiating circuit 11. The differential output signal from the differential circuit 11 is applied to a zero cross detection circuit 12 and a level slice circuit 13. The level slice circuit 13 slices the positive and negative levels of the differential output signal at predetermined positive and negative slice levels, and sends the positive output signal d to the cent terminal S of the flip-flop 14 and the negative output signal e to the reset terminal of the flip-flop 14. In addition to each R,
The Q terminal output signal f of the flip-flop 14 and the detection signal C of the zero cross detection circuit [2] are added to the AND circuit 15, and the AND output signal is used as the output pulse signal g.

FIG. 3 is an explanatory diagram of the operation of the embodiment of the present invention.
(g) shows an example of the signal waveform of the signal 3-g at each part in FIG. If the input analog signal a is a positive or negative polarity signal as shown in fa), and "0" is a 0 level, the negative polarity signal is also converted to a positive polarity signal by the absolute value circuit IO. and differentiated by the differentiating circuit 11, we get
A differential output signal with a solid waveform shown in (b) is obtained. This differential output signal S has a slope waveform that slopes downward to the right during a period corresponding to the peak point of the input analog signal a.

The zero-crossing detection circuit 12 detects the zero-crossing point of the differential output signal of this solid waveform.The zero-crossing point of the waveform rises at the point where the differential output signal goes below the 0 level, and then falls at the point where it exceeds the O level. The detection signal C is output as shown in (C1).
Although not shown in the period ``, the differential output signal contains low-level positive and negative polarity signals, and zero-cross detection will be performed for this noise component as well. , the signal is unrelated to the peak point of the input analog signal a.

In addition, the level slice circuit 13 slices the differential output signal s of the solid line waveform using the positive and negative slice levels SLI and SL2 in FIG. 3(b), and the positive side output signal d due to the slice level SLI is ( d), the negative side output signal e due to slice level SL2 is as shown in fQ). Therefore, the Q terminal output signal r of the flip-flop 14 is set by the positive output signal d and reset by the negative output signal e, resulting in the signal shown in (f).

The AND circuit 15 generates an output pulse signal g shown at +g+ of the AND output of the zero cross detection signal C shown in (C) and the Q terminal output signal r of the flip-flop 14 shown in (f).
will be output. That is, it is possible to obtain an input analog (an output pulse signal corresponding to the peak point of No. i a).

In the above-mentioned differentiating circuit 11, the case is shown in which a differentiated output signal with a solid line waveform (bl) is output, but in addition to this differentiated output signal with a solid line waveform, all differential output signals with a dotted line waveform having a phase difference of 180 degrees are output. By configuring to output , it is possible to perform slicing using one type of slice level SL1.That is, when the input analog signal a is a balanced signal, it is converted to an absolute value by the absolute value circuit 10, and the differential circuit 11 converts it into an absolute value.
When differentiated by , a differentiated output signal shown by the solid line and dotted line in (bl) in FIG. 3 is obtained, making it easy to set the slice level.

FIG. 4 is a circuit diagram of an embodiment of the present invention, and shows a case where the input analog signal of a balanced signal as described above is manually input.

In the same figure, 01-C3 are capacitors, R1-R12
is a resistor, Ql-C8 is a transistor, CMP 1 to CM
P3 is a comparison circuit, FF is a flip-flop, G is a gate circuit, VSL is a slice level power supply, VCl: +
VE! is the power supply voltage.

An absolute value circuit 10 is configured by transistors Ql and Q2, and includes a resistor R3, a capacitor C3, and transistors Ql and Q.
2. A differentiating circuit 11 is configured by Q8. Also, transistor Q3. Q4 constitutes an emitter follower circuit for applying the output signal of the differentiating circuit to the comparison circuits CMP1 to CMP3, and the L transistors Q5 to Q7 constitute constant current sources. Therefore, capacitors C1 to C3 and resistor R
1 to R12 and transistors 01 to Q8 constitute the absolute value differentiating circuit 1 in FIG.

Furthermore, the comparison circuits CM and P1 constitute the zero-cross detection circuit 12, and the comparison circuits CMP2. CMP3 constitutes a level slice circuit 13, and a single slice level is set by a slice level power supply VSL. Also flip flop F
F corresponds to the flip-flop 14, and gate circuit G corresponds to the AND circuit 15, respectively.

The planar input analog signal is applied to the bases of transistors Ql and Q2 via capacitors CI and C2, converted into an absolute value signal, and differentiated according to a time constant by resistor R3 and capacitor C3, resulting in a differential output of the balanced input analog signal. The signal will appear on the resistor R4R5, and will be passed through the emitter follower circuit formed by the transistor Q3°C4.
It is added to comparison circuits CMP1 to CMP3.

The zero cross detection circuit 12 can also be configured with two comparison circuits that compare each balanced differential output signal with a 0 level, but in this embodiment, the balanced differential output signal is connected to a child terminal and one terminal. 1 comparison circuit CM added to
It is composed of P1. That is, the differential output signal of the solid line waveform in FIG. 3(b) is applied to one terminal, and the differential output signal of the dotted line waveform is applied to the + terminal for comparison.
At the zero-crossing point, both are at the same level, so the output signal is as shown in FIG. 3(C).

Also, the differential output signal of the solid waveform in (bl in FIG. 3) is applied to the child terminal of the comparator circuit CMP2, and the slice level is added to one terminal, so the output signal is as shown in f in FIG.
It will be as shown in dl. Also, the differential output signal of the dotted line waveform in (bl in Fig. 3) is applied to the child terminal of the comparator circuit CMP3, and the slice level is added to one terminal, so the output signal is as shown in (e) in Fig. 3. It will be shown.

Therefore, since the flip-flop FF is set by the output signal of the comparator circuit CMP2 and reset by the output signal of the comparator circuit CMP3, the Q terminal output signal becomes the one shown in parentheses in FIG. Circuit G is
Output signal of comparison circuit CMPI and flip-flop FF
A balanced output pulse signal of non-inversion and inversion of the AND output with the Q terminal output signal is output, and a balanced output pulse signal corresponding to the peak point of the input analog signal can be obtained.

The above embodiment mainly shows the case where the read signal of the magnetic head is an input analog signal, but it also corresponds to the peak point in bipolar signal reception processing in data transmission, clock signal extraction, etc. It can also be applied to the formation of pulses.

〔Effect of the invention〕

As explained above, the present invention includes the absolute value differentiating circuit 1,
It includes a zero cross detection circuit 2, a level slice circuit 3, a flip-flop 4, and a gate circuit 5, and outputs a pulse signal corresponding to the peak point of the input analog signal, and differentiates the absolute value of the input analog signal. The signal is sliced at a predetermined level by the level slicing circuit 3. Therefore, for example, when the read signal of a magnetic head is an input analog signal, crosstalk components consisting of relatively low-frequency components are not included. However, by differentiating it, the effect can be reduced. Therefore, there is an advantage that the slice level can be easily set.

Furthermore, by differentiating the absolute value of the human-powered analog signal, the slope direction of the waveform of the zero-crossing point of the differentiated output signal corresponding to the position of the peak point of the input analog signal becomes the same, making it easy to detect the accurate zero-crossing point, and increasing the There is also an advantage in that a pulse signal corresponding to the peak point of the recording density read signal can be formed without error.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of the operation of an embodiment of the present invention.
FIG. 4 is a circuit diagram of an embodiment of the present invention, FIG. 5 is a block diagram of a conventional example, and FIG. 6 is an explanatory diagram of the operation of the conventional example. 1 is an absolute value differential circuit, 2 is a zero cross detection circuit, 3 is a level slice circuit, 4 is a flip-flop, and 5 is a gate circuit.

Claims (1)

[Claims] An absolute value differentiating circuit (
1), a zero-crossing detection circuit (2) for detecting a zero-crossing point of the output signal of the absolute value differentiating circuit (1), and slicing the positive and negative levels of the output signal of the absolute value differentiating circuit (1) at a predetermined slice level. and a flip-flop (4) that is set by the positive output signal of the level slice circuit (3) and reset by the negative output signal.
and a gate circuit (5) that adds the output signal of the flip-flop (4) and the output signal of the zero-cross detection circuit (2) and outputs a pulse corresponding to the peak point of the input analog signal. A pulsing circuit characterized by: