JPH02145018A - Level shift circuit - Google Patents

Abstract

PURPOSE:To decrease the layout area and to attain high speed processing by connecting an on-resistance control transistor (TR) in series with a load side TR. CONSTITUTION:The circuit consists of an inverter 20, enhancement N-channel MOS transistors (TRs) 10, 11, enhancement P-channel MOS TRs 14, 15 receiving a complementary signal to its gate as loads of the TRs 10, 11, and P-channel MOS TRs 12, 13 connected in series with the P-channel MOS TRs 14, 15 and whose gate and drain are connected in crossing. Thus, it is possible to decrease the size of the TRs 10, 11 to nearly 1/3. Since gates of the TRs 12, 14 (or TRs 13, 15) are arranged side by side, the considerable reduction of the area as a whole is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a level shift circuit, and particularly to a level shift circuit that can reduce the layout area and is suitable for high speed operation.

[Prior Art] Conventionally, a circuit shown in FIG. 4 is known as this type of level shift circuit. an inverter 20 that generates an inverted signal;
It is composed of an N-channel type MO transistor 10゜11 whose gate is connected to a complementary signal and whose source is grounded, and a P-channel type MO transistor 12.13 whose gates and trains are cross-connected and connected as a load. There is.

Next, the operation of this circuit will be explained. Assuming that the signal input from the input terminal 4 is S, S is inverted by the Cl'VIOS inverter 20 to create a negative signal, and the signals 'ff and S are supplied to the gates of N-channel MOS transistors 10 and 11, respectively. Since the signal S or S is a signal between power supply terminals 2 and 3, power supply terminal 2 is connected to the ground level GND (O
volts) and the power supply terminal 3 is ■3 volts, the signal S, ``ff!, ts=V3゜not=0 or S=O,
= V3. Therefore, the operations of transistors 10 and 11 are as shown in the table below.

However, the threshold voltage VTN of N-channel MOS transistors 10 and 11 is set to V3>VTN>O, and the power supply terminal 1
is ■1 volt. Therefore, consider a state in which the transistor 10 changes from off to on and the transistor 11 changes from on to off. Transistor 10 off, transistor 1
When the transistor 1 is on, the transistor 12 is on and the transistor 13 is off. Here, when the transistor 10 changes from off to on and the transistor 11 changes from on to off, both transistors 10 and 12 are in the on state.
Transistors 11 and 13 are both turned off. Therefore, the output terminal 5 remains at a low level and does not change immediately. On the other hand, since transistors 10 and 12 are both in the on state, if the on-resistance of transistor 10 is smaller than the on-resistance of transistor 12, the potential at node 6 decreases, transistor 13 is turned on, and the potential at output terminal 5 increases, and the transistor The on-resistance of transistor 12 increases, the potential at node 6 further decreases, the on-resistance of the transistor decreases, positive feedback is applied, and finally transistor 12 turns off and transistor 13 turns on. Therefore, the output terminal 5 changes from low level to high level.

It works exactly the same way in the opposite case. After all, in the circuit shown in Figure 1, when N-channel MOS transistor 10 (or 11) is turned on, its on-resistance is P-channel MOS transistor 10 (or 11).
) It is important that the on-resistance of transistor 12 (or 13) is sufficiently smaller, otherwise the output terminal 5
The 0 level remains unchanged.

[Problems to be Solved by the Invention] In the conventional level shift circuit described above, the N-channel MOS l transistor 10 (or 11) is used as described above.
and P channel MOS) transistor 12 (or 13)
To explain this quantitatively below, when both transistor 10 (or 11) and transistor 12 (or 13) are turned on, the potential of node 6 (or output terminal 5) In order to decrease the drain current value IDl0. of the transistor 10.12 (or 11.13). ID12 (IDI 1. ID13)
ID10>ID12 (or IDII>ID1)
3) The following conditions must be satisfied.

Therefore, ID 10=10 (V3-VTN)2>ID
l2=to12 (Vl-IVTPI)2(KIO.

(12 is the conductivity coefficient of transistor 10.12.

), so in the end ■gu10/ni12>, (Vl-IVTP
l )”/ (V3-VTN) becomes 2. Sokote V1
=5v, V3=2v, I VTP l =0.5v.

If VTN=0.8v, K 10/K 12> 1
It becomes 4.06.

If we look at the double margin, I(] C1/K 1
2>28.12.

Normally, N-channel MO5 has about twice the carrier mobility, so W/Ll is the gate width.

(L is the gate length), (W/L) +
2/(W/L)+2>14.

Therefore, the area occupied by the N-channel MOS transistors 10 and 11 becomes large, and a large layout area is required.

Furthermore, since the gate capacitance of the N-channel MOS transistors 10 and 11 also increases, there is a drawback that the transistors in the driver and inverter 20 in the previous stage must be made larger in order to ensure speed.

[Difference between the present invention and the prior art] The present invention differs from the conventional level shift circuit described above in that an on-resistance control transistor is connected in series with the load side transistors 12 and 13.

[Means for Solving the Problems] The gist of the present invention is to provide a first field effect transistor of a first conductivity type and a second field effect transistor of a first conductivity type, each of which has a pair of complementary signals supplied to its gate.
A first field effect transistor comprising a field effect transistor, a third field effect transistor of a second conductivity type, and a fourth field effect transistor connected to the train of the first field effect transistor.
a series circuit, a fifth field effect transistor of a second conductivity type connected to the drain of the second field effect transistor, and a sixth field effect transistor.
a second series circuit consisting of a field effect transistor, the gate of the third field effect transistor is connected to the train of the second field effect transistor, and the gate of the fifth field effect transistor is connected to the train of the first field effect transistor. The transistors are connected to a train of transistors, and the pair of complementary signals are supplied to the gates of the fourth field effect transistor and the sixth field effect transistor, respectively.

[Example] FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

An inverter 20 that generates an inverted signal, an enhancement N-channel type rv'ros transistor 14.15 that uses the complementary signal as a gate input, and an enhancement N-channel N40S transistor that uses the complementary signal as a gate input; and P
Channel type MO9) P-channel MOS transistors 12 and 13 are connected in series to transistors 14 and 15, and their gates and drains are cross-connected. Assuming that the signal S is given from the input terminal 4, the result will be as shown in the table below.

Here, the operation when the signal S changes from ■3 to Ov will be explained. At this time, the transistor 1o changes from off to on, and the transistor 11 changes from on to off. Therefore, since transistors 11 and 13 are both off, output terminal 5 remains at a low level. On the other hand, the transistor 10,
Since transistors 12 and 14 are both in the on state, if the on-resistance of transistor 10 is smaller than the sum of the on-resistances of transistors 12 and 14, the potential at node 6 starts to drop.

Therefore, the transistor 13 is turned on and the potential of the output terminal 5 rises. Further, the on-resistance of the transistor 12 increases, and the potential effect at the node 6 is promoted.

In this way, positive feedback works, and finally the output terminal 5 settles to a high level (VIV) and the node 6 to a low level (Ov). A similar operation occurs when the signal S changes from OV to V3v. In this embodiment, transistors 10, 11, 12, 14,
Reference numerals 13 and 15 constitute first to sixth field effect transistors, respectively.

Next, as in the conventional example, a quantitative understanding will be attempted.

Transistors 10, 12, 14 (or transistor 1
1.131 1!5) are both turned on, node 6
In order for the potential of output terminal 5 to drop, IDl
0>ID]4=ID12 (ID10, ID12.ID
14 is the drain current of transistor 10°12.14)
It is necessary that the following conditions hold true. Here, assuming that the on-resistance of transistor 12 (or transistor 13) is negligibly smaller than that of transistor 14 (or transistor 15), ID 10=10 (V3-VTN) 2> ID
I4=14 (Vl-V3-I VTP I)
2 (KIO, 14 is transistor 10, 14
).

Therefore, K 10/K 14> (V 1-V3- I
VTP l ) 2/ (V3-VTN) 2, and similarly ■1-=5v, V3=2v, IVTPI=0
．． 5v.

When VTN=0.8v, K10/K14>4°34. If you see a double margin, KIO/to 1
4>8.68. Normally, carrier mobility in N-channel MO8 is about twice as high, so considering the ratio of W/L, (W/L)+s/(W/L)1t>4. 34
becomes. In the end, the transistor compared to the conventional circuit is 10.11
can be reduced to about 1/3 of the size. Although transistors 14 and 15 are added, the layout is similar to transistors 12 and 14 (or transistors 13 and 15).
), since the gate electrodes can be arranged side by side, the area increases only slightly, and the overall area can be significantly reduced.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention. In this embodiment, transistors 14 and 15 are transistors 12 and 12.
The difference is that it is connected to the drain side of No. 13. The circuit operation is exactly the same as in the first embodiment. In this embodiment, transistors 10°11.12.14, 13. ．． 35
constitute the first to sixth field effect transistors, respectively. FIG. 3 is a circuit diagram showing a third embodiment of the present invention. This embodiment is a source follower N-channel MOS in which a complementary human input signal is used as a gate input in the circuit of the first embodiment.
This is a circuit to which transistors 16 and 17 are added.

Transistors 16 and 17 are circuits for speeding up when the level shift circuit is inverted. The operation will be explained below. Similarly, consider the operation when the number of signals changes from V3 to Ov. At this time transistor 10
．． The transistor 16 changes from off to on, and the transistor 11 changes from on to off. Therefore, as explained in the first embodiment, the potential at node 6 begins to drop. roughly transistor 11
Since both ゜13 are off and the output terminal 5 remains at a low level, the transistor 16 is turned on, raising the potential of the output terminal 5, and the transistor ゜3 is also turned on,
The potential rise of the output terminal 5 is accelerated. At this time, turning on the transistor 16 has the effect of lowering the potential at the node 7, thereby accelerating the potential drop at the node 6. Therefore, similarly, positive feedback is applied in the direction that the on-resistance of the transistor 12 becomes smaller and the on-resistance of the transistor 130 becomes larger, and finally the output terminal 5 becomes a high level (vl).
, the potential at node 6 settles to a low level (Ov). At this time, the transistor 16 is turned off. As explained above, by adding the transistors 16 and 17, the change in potential at the output terminal 52 node 6 is accelerated, and the operating speed can be further increased.

[Effects of the Invention] As explained above, the level shift circuit of the present invention has the advantage that the layout area can be reduced and the speed can be increased.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first embodiment of the invention, FIG. 2 is a circuit diagram showing a second embodiment of the invention, and FIG. 3 is a circuit diagram showing a third embodiment of the invention.
A circuit diagram showing an embodiment, and FIG. 4 is a circuit diagram showing a conventional example. 1 ・ ・ ・ 2 ・ ・ ・ 3 ・ ・ 4 ・ ・ ・ 5 ・ ・ 10, 1 12 to 15 ・ ・ ・ 20 ・ ・ ・ 1st power terminal, ・ 2nd power terminal, ・Third power supply terminal, ...input terminal, ...output terminal, enhancement N-channel MOS transistor, enhancement N-channel MOS) transistor, ...inverter. Patent applicant Kiyoshi Kuwai, agent for NEC Corporation, patent attorney - Figure 3 Figure 4

Claims (1)

[Claims] A first field effect transistor and a second field effect transistor of a first conductivity type, each of which has a pair of complementary signals supplied to its gate, and a second field effect transistor of a second conductivity type connected to the drain of the first field effect transistor. a first series circuit consisting of a third field effect transistor and a fourth field effect transistor, and a second series circuit connected to the drain of the second field effect transistor.
a second series circuit including a fifth field effect transistor and a sixth field effect transistor of conductivity type, the gate of the third field effect transistor being connected to the drain of the second field effect transistor, and the gate of the third field effect transistor being connected to the drain of the second field effect transistor; The gates of the field effect transistors are connected to the drains of the first field effect transistor, and the pair of complementary signals is supplied to the gates of the fourth field effect transistor and the sixth field effect transistor, respectively. A level shift circuit featuring: