JPH02145444U - - Google Patents

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Publication number
JPH02145444U
JPH02145444U JP5317989U JP5317989U JPH02145444U JP H02145444 U JPH02145444 U JP H02145444U JP 5317989 U JP5317989 U JP 5317989U JP 5317989 U JP5317989 U JP 5317989U JP H02145444 U JPH02145444 U JP H02145444U
Authority
JP
Japan
Prior art keywords
terminal
level
driver
signal
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5317989U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5317989U priority Critical patent/JPH02145444U/ja
Publication of JPH02145444U publication Critical patent/JPH02145444U/ja
Pending legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの考案による実施例の回路図、第２
図〜第５図は第１図の動作説明図、第６図はＣＰ
ＵとＩＣＥ用プローブの接続方法説明図である。 １……ドライバ、２……抵抗、３……レベル検
器、４Ａ，４Ｂ……抵抗、５……ドライバ、６…
…制御回路、７……プローブ、７Ａ……Ｆ端子（
フロート端子）、７Ｂ……接地端子、８……ＣＰ
Ｕ、８Ａ……Ｆ端子、９……抵抗、１０……プリ
ント板。 Figure 1 is a circuit diagram of an embodiment according to this invention, Figure 2
Figures 5 to 5 are explanatory diagrams of the operation of Figure 1, and Figure 6 is CP.
It is an explanatory diagram of the connection method of U and the ICE probe. 1... Driver, 2... Resistor, 3... Level detector, 4A, 4B... Resistor, 5... Driver, 6...
...Control circuit, 7...Probe, 7A...F terminal (
float terminal), 7B...ground terminal, 8...CP
U, 8A...F terminal, 9...Resistor, 10...Printed board.

Claims (1)

【実用新案登録請求の範囲】 制御信号１１を入力とし、抵抗２を介してＦ端
子８Ａのレベルを制御するドライバ１と、 Ｆ端子８Ａのレベルと基準電圧との大小を比較
し、レベル検出信号１２を出力とするレベル検出
器３と、 制御信号１３を入力とし、Ｆ端子８Ａのレベル
を制御するドライバ５とを備えることを特徴とす
るＦ端子と電源間の抵抗有無検出制御回路。[Claims for Utility Model Registration] A driver 1 which receives a control signal 11 as an input and controls the level of an F terminal 8A via a resistor 2, compares the level of the F terminal 8A with a reference voltage, and generates a level detection signal. 1. A control circuit for detecting the presence or absence of a resistance between an F terminal and a power source, characterized in that it is equipped with a level detector 3 having a signal 12 as an output, and a driver 5 receiving a control signal 13 as an input and controlling the level of the F terminal 8A.
JP5317989U 1989-05-09 1989-05-09 Pending JPH02145444U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5317989U JPH02145444U (en) 1989-05-09 1989-05-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5317989U JPH02145444U (en) 1989-05-09 1989-05-09

Publications (1)

Publication Number Publication Date
JPH02145444U true JPH02145444U (en) 1990-12-10

Family

ID=31574143

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5317989U Pending JPH02145444U (en) 1989-05-09 1989-05-09

Country Status (1)

Country Link
JP (1) JPH02145444U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0277986A (en) * 1988-09-14 1990-03-19 Hitachi Ltd Semiconductor integrated circuits and emulators

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0277986A (en) * 1988-09-14 1990-03-19 Hitachi Ltd Semiconductor integrated circuits and emulators

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