JPH02146475U - - Google Patents

Info

Publication number
JPH02146475U
JPH02146475U JP5529689U JP5529689U JPH02146475U JP H02146475 U JPH02146475 U JP H02146475U JP 5529689 U JP5529689 U JP 5529689U JP 5529689 U JP5529689 U JP 5529689U JP H02146475 U JPH02146475 U JP H02146475U
Authority
JP
Japan
Prior art keywords
printed wiring
wiring board
pad portion
lead wires
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5529689U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5529689U priority Critical patent/JPH02146475U/ja
Publication of JPH02146475U publication Critical patent/JPH02146475U/ja
Pending legal-status Critical Current

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Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図aは本考案の一実施例に係るプリント配
線板のパツド部の拡大斜視図、第1図bはパツド
部にリード線を半田付けした状態を示す第1図a
のA−A断面図、第2図aは従来の表面実装用I
Cとプリント配線板のパツド部の拡大図、第2図
cはパツド部にリード線を半田付けした状態を示
す第1図bのB−B断面図である。 1:プリント配線板、2:パツド部、2a,2
b:パツド、3a:リード線、4……半田、4a
:半田フイレツト部。
Fig. 1a is an enlarged perspective view of a pad portion of a printed wiring board according to an embodiment of the present invention, and Fig. 1b shows a state in which lead wires are soldered to the pad portion.
A-A sectional view of , Figure 2a is a conventional surface mount I
FIG. 2C is an enlarged view of the pad portion of the printed wiring board, and FIG. 2C is a sectional view taken along the line BB in FIG. 1: Printed wiring board, 2: Pad part, 2a, 2
b: Padded, 3a: Lead wire, 4...Solder, 4a
:Solder fillet part.

補正 平1.8.2 図面の簡単な説明を次のように補正する。 明細書第6頁第6行目「表面実装用IC」の後
の「と」を削除し、「を示す図、第2図bは従来
の」を挿入する。
Amendment 1.8.2 The brief description of the drawing is amended as follows. In the 6th line of page 6 of the specification, the ``and'' after ``Surface Mount IC'' is deleted, and ``A figure showing the figure, Figure 2b is a conventional'' is inserted.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数のリード線を有する表面実装用ICを搭載
するためにパツド部を配設したプリント配線板に
おいて、このプリント配線板のパツドの一端をリ
ード線の横幅よりも広く形成し、これを交互に組
合せて配設するパツド部を有することを特徴とす
るプリント配線板。
In a printed wiring board provided with a pad portion for mounting a surface mount IC having multiple lead wires, one end of the pad of the printed wiring board is formed wider than the width of the lead wires, and these are alternately combined. What is claimed is: 1. A printed wiring board characterized in that it has a pad portion disposed on the board.
JP5529689U 1989-05-16 1989-05-16 Pending JPH02146475U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5529689U JPH02146475U (en) 1989-05-16 1989-05-16

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5529689U JPH02146475U (en) 1989-05-16 1989-05-16

Publications (1)

Publication Number Publication Date
JPH02146475U true JPH02146475U (en) 1990-12-12

Family

ID=31578120

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5529689U Pending JPH02146475U (en) 1989-05-16 1989-05-16

Country Status (1)

Country Link
JP (1) JPH02146475U (en)

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