JPH02146624A - Detecting system for external synchronizing signal - Google Patents

Abstract

PURPOSE:To facilitate the operation of a processor and to improve the process step efficiency by performing the program execution control with use of a synchronous flag which is set just with the rise of an external synchronous signal and then reset automatically after execution of a synchronization detecting instruction. CONSTITUTION:A rise edge detecting part 1 is prepared together with a processor processing instruction memory part 4, a program counter 3, a decoder 5, a program sequence control part 6, and a flag register 7. A program is executed with control by a synchronous flag which is set just with the rise of an external synchronous signal FL and then reset automatically after execution of a synchronization detecting instruction. Thus the signal FL can be detected without issuing a clear instruction to the register 7 via a program at detection of the signal FL.

Description

[Detailed Description of the Invention] [Summary] Regarding an external synchronization signal detection method for detecting an external synchronization signal of a digital signal processor, etc. that performs periodic processing such as audio signal processing, when an external synchronization signal is detected, a program is written to a flag register. The purpose is to enable the detection of an external synchronization signal without issuing a clear command when the external synchronization signal is set. It is configured to control program execution using a controlled synchronization flag.

[Industrial Field of Application] The present invention relates to an external synchronization signal detection method for detecting an external synchronization signal of a digital signal processor or the like that performs periodic processing such as audio signal processing.

Generally, in audio signal processing and the like, it is necessary to accurately detect an external synchronization signal and control the execution of a program within a processor. For this purpose, as shown in FIG. 5, an external synchronization signal *FL is detected by an external synchronization signal detection section 100, and a signal to that effect is supplied to a digital signal processor (DSP) 101. When the external synchronization signal *FL is detected in this manner, the digital signal processor 101 takes in digital data from the A/D converter 103 and performs necessary processing (for example, filtering processing) on this data.

[Prior Art] FIG. 3 is a block diagram of a conventional external synchronization signal detection section. In this FIG. 3, 1 is a rising edge detection section (RED); It receives the signal *FL and detects its rising edge.

Reference numeral 2 denotes an instruction ROM (IROM) as a processor processing instruction storage unit, and this instruction ROM 2 stores instructions to be processed by the processor.

3 is a program counter (pc), and this program counter 3 gives an address of the instruction ROM 2.

4 is an instruction register (IR), and this instruction register 4 is
It takes in (fetches) instructions issued from the instruction ROM 2.

5 is a decoder (DEC), and this decoder 5 decodes the code from the instruction register 4 to generate a control signal within the digital signal processor 101.

6 is a program sequence control section (SEQ), and this program sequence control section 6 is for controlling the program counter 3 by being controlled by the decoder 5.

7 is a flag register (FLG), and this flag register 7 sends an external synchronization signal * to the program sequence control unit 6.
This is to notify that the FL has been accepted.

With this configuration, when the rising edge detecting section 1 receives the external synchronizing signal *FL, the rising edge detecting section 1 detects the rising edge of the external synchronizing signal *FL, and
Its output SFL falls to a low level. Then, this signal SFL is input to the set end of the flag register 7, and on the condition that the clear signal CLFL from the decoder 5 is not at a low level, that is, there is no conflict, the flag signal FLG is input from the flag register 7. becomes high level.

Then, when the flag signal FLG becomes high level, the program sequence control section 6 instructs the program counter 3 to a branch address, and the program counter 3 specifies the address to the instruction ROM 2. As a result, an instruction corresponding to the address from the instruction ROM 2 (for example, an instruction to fetch data from an A/D converter) is stored in the instruction register 4, and this is further decoded by the decoder 5 to be sent to the digital signal processor 1.
Generates a control signal within 01.

Note that when the flag signal FLG is at a low level, an instruction (BRUL FLG) to branch to address n if FLG≠1 is issued from the instruction ROM 2.

n) has been taken out, and the program counter 3 is repeating n and n+1.

Timing diagrams of each signal according to such a conventional example are shown in FIGS. 4(a) to 4(g).

[Problems to be Solved by the Invention] However, in such a conventional external synchronization signal detection method, when a rising edge of the external synchronization signal *FL is received, the flag register 7 is always set, and the
In the case of the figure, it is necessary to reset the flag register 7 once in the previous step), so a program instruction to clear the flag register 7 by a program instruction is required as a processor instruction, and this clear instruction is also included in the processing step. This is necessary in the program [see the instruction CLRFLG in Figure 4(c) and the low level part of the signal CLFFL in Figure 4(d)], so applications that use synchronization detection frequently (for example, audio signal processing) However, there is a problem that the existence of this clear processing step increases the processing time.

Furthermore, as shown in FIGS. 4(d) and 4(f), the signal S F I from the rising edge detector 1 and the clear signal C
There will also be a timing when the set signal and the reset signal to the flag register 7 conflict with each other, and in consideration of this case, conventionally, a function has been provided to give priority to one of the signals. Must.

The present invention was made in view of these problems, and
It is an object of the present invention to provide an external synchronization signal detection method that makes it possible to detect an external synchronization signal without issuing a clear instruction in a program to a flag register when detecting the external synchronization signal.

[Means for Solving the Problems] For this reason, the external synchronization signal detection method of the present invention includes a rising edge detection section, a processor processing instruction storage section, a program counter, a decoder, a program sequence control section, and a flag register. In this case, the synchronization flag is set only at the rising edge of the external synchronization signal and is dynamically reset after the synchronization detection command is executed.
It is characterized by controlling program execution.

[Function] With this configuration, when the rising edge of the external synchronization signal is detected, the synchronization flag is set, and then the synchronization detection command is executed based on this set information. The synchronization flag is automatically reset, but program execution control is performed using the synchronization flag controlled in this way.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. The embodiment shown in FIG. an instruction ROM (processor processing instruction storage unit) 2 for storing instructions to be processed, a program counter 3 for giving the address of the instruction ROM 2, an instruction register 4 for taking in instructions issued from the instruction ROM 2, and a code for decoding the code from the instruction register 4. a decoder 5 that generates a control signal in the digital signal processor 101;
It is provided with a program sequence control section 6 for controlling a program counter controlled by a decoder 5, and a flag register 7 that notifies the program sequence control section 6 that an external synchronization signal *FL has been received. The difference is that program execution is controlled using a synchronization flag that is set only at the rising edge of the external synchronization signal *FL and is dynamically reset after execution of a synchronization detection command.

That is, the instruction from instruction register 4 is BRULFLG,n
(If FLG≠1, the instruction branches to address n), and while BRUL FLG, n continues, the decoder 5
The signal BRFL is output as a high level signal from
In response to this, the program sequence control unit 6 outputs the signal B.
Input the flag enable signal FLEN, which automatically rises in conjunction with the rise of RFL and automatically falls in conjunction with the fall of the signal BRFL after execution of the synchronization detection command, to the reset terminal of the flag register 7. By doing so, the above control is realized.

Next, the operation will be explained. First, the instruction from instruction register 4 changes to BRUL FLG,n, then BR
While UL FLG,n continues, the signal B is output from the decoder 5.
RF T- is output as a high level signal,
In response to this, the flag enable signal FLEN from the program sequence control section 6 automatically rises in conjunction with the rising of the signal BRFL, and is inputted to the reset terminal of the flag register 7 as a high level signal.

Then, the rising edge detection section 1 detects the external synchronization signal *F.
When L is received, the rising edge detection unit 1 detects the rising edge of the external synchronizing signal *FL, and outputs the signal SFL.
falls to a low level. Then, this signal SFL is input to the set terminal of the flag register 7, and at this time, since the high-level flag enable signal FLEN is input to the reset terminal of the flag register 7, the flag signal FLG is input from the flag register 7. Become a high level.

Then, when the flag signal FLG becomes high level, the program sequence control section 6 instructs the program counter 3 to a branch address, and the program counter 3 specifies the address to the instruction ROM 2. As a result, an instruction corresponding to the address from the instruction ROM 2 (for example, an instruction to fetch data from an A/D converter) is stored in the instruction register 4, and this is further decoded by the decoder 5 to be sent to the digital signal processor 1.
Generates a control signal within 01.

By the way, the instruction content of instruction register 4 is BRULFL.
When G and n are no longer present, the signal B RF L falls to a low level, and the flag enable signal FLEN also falls to a low level in conjunction with this. This causes flag register 7
is automatically reset, flag signal FLG falls to low level, and waits for the next rise of external synchronization signal *FL.

Incidentally, timing diagrams of each signal according to this embodiment are shown in FIGS. 2(a) to 2(h).

In this way, the flag enable signal FLEN indicating that the synchronization signal is being detected is generated from the signal BRFL input from the decoder 5, and the flag register 7 is set only when the flag enable signal FLEN is at a high level. Therefore, when performing synchronization detection, only the rBRUL FLG and nJ instructions need to be prepared as processing steps. As a result, there are significant advantages in terms of ease of use of the processor and efficiency of processing steps.

[Effects of the Invention] As detailed above, according to the external synchronization signal detection method of the present invention, control is performed such that the external synchronization signal is set only when the external synchronization signal rises, and is dynamically reset after the synchronization detection command is executed. Since the program execution is controlled using the synchronization flag, it has the advantage that improvements in ease of use of the processor and efficiency of processing steps can be achieved with small-scale changes.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 (
a) to (h) are timing diagrams according to an embodiment of the present invention, Fig. 3 is a block diagram showing a conventional example, Fig. 4 (a) to (g) are timing diagrams according to a conventional example, and Fig. 5 is an audio diagram. FIG. 2 is a block diagram of a signal processing device. In the figure, 1 is a rising edge detection unit, 2 is an instruction ROM (processor processing instruction storage unit), 3 is a program counter, 4 is an instruction register, 5 is a decoder, 6 is a program sequence control unit, 7 is a flag register, and 100 is a External synchronization signal detection section, 101 is a digital signal processor, 102 is an A/
It is a D converter.

Claims (1)

[Claims] A rising edge detection unit (1) that receives an external synchronization signal and detects its rising edge, and a processor processing instruction storage unit (2) that stores instructions to be processed by the processor.
a program counter (3) that provides an address of the processor processing instruction storage section (2); an instruction register (4) that takes in an instruction issued from the processor processing instruction storage section (2); and the instruction register (4). a decoder (5) that decodes a code from the processor to generate a control signal in the processor; and a program sequence control unit (6) for controlling a program counter controlled by the decoder (5). is equipped with a flag register (7) that indicates that the external synchronization signal has been received, and the synchronization flag is controlled so that it is set only at the rising edge of the external synchronization signal and automatically reset after the execution of the synchronization detection command. An external synchronization signal detection method characterized by controlling program execution.