JPH02146745A - Semiconductor element and manufacture thereof - Google Patents

Abstract

PURPOSE:To secure Roff which is equivalent to an insulating material as amorphous silicon and utilize effect of reduction in Ron due to inclusion of impurities ion by forming a semiconductor element constituting an antifuse in four-layer structure of a lower-part electrode, amorphous silicon, a silicon insulation film, and an upper-part electrode. CONSTITUTION:A semiconductor which allows the area between one electrode 104 and the other electrode 106 to change from high-resistance state to low- resistance state by applying voltage between the electrodes 104 and 106 formed on the surface of a semiconductor substrate 101 for making a current flow is in four-layer structure consisting of the upper-part electrode 106, an amorphous silicon 105, a silicon oxide insulation film 107, and a lower-part electrode 102. For example, the impurities diffusion layer 102 is formed at the Si semiconductor device 101 and an interlayer insulation film 103 is formed over the entire surface, and then a contact hole 108 is formed. Then, SiO2 is accumulated by 100Angstrom or less and the amorphous silicon 105 is formed on it for patterning. Then, an interlayer insulation film 103a is accumulated over the entire surface and contact holes 108a and 109 are formed, and then the wiring electrode 104 and the upper-part electrode 106 are formed.

Description

[Detailed Description of the Invention] [Industrial Application Field 1] The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to a semiconductor device and a method for manufacturing the same. The so-called "anti fuse"
The present invention relates to a semiconductor device that primarily functions as a semiconductor device and a method for manufacturing the same.

[Conventional technology]

The above-mentioned untie fuse is used by applying a function in which when a voltage is applied to an electrode of a semiconductor element and a current is caused to flow, the electrode changes from a non-conductive state to a conductive state. In other words, an untied fuse forms a semiconductor element that has the opposite characteristics or function to the conventional fuse, which breaks a polycrystalline silicon wiring and changes it from a conductive state to a non-conductive state. be.

Conventionally, chalcogenide, amorphous silicon, and the like have been known as substances that serve as antifuses, and practical examples thereof include those disclosed in the following documents. Below, we will briefly explain the antithetical features shown in these documents.

Document 1/Japanese Patent Publication No. 47-32944: An amorphous high-resistance semiconductor material is brought into a low-resistance stable state rather than a high-resistance stable state by applying energy such as electron irradiation or laser irradiation.

Literature 2. Japanese Patent Publication No. 57-4038: A PROM device whose constituent elements are high-resistance polycrystalline silicon whose resistance value changes irreversibly depending on an applied electric field.

Document 3: Japanese Unexamined Patent Publication No. 54-88739... An EEFROM device whose component is tellurium-based chalcogenide, which has high electrical resistance in an amorphous state and low electrical resistance in a crystalline state.

The above untied fuse is used for IC
Simple wiring connection switch inside, PLA (programmable logic array), memory redundant circuit, and FR
It has been applied to OM, etc., and its application is being considered.

FIG. 2 is a schematic cross-sectional view of a main part showing the structure of a semiconductor element that is used as the above-mentioned antifuse and is most similar to the semiconductor element of the present invention.

In the figure, 201 is a semiconductor substrate, 202 is an impurity diffusion layer formed on the surface of the semiconductor substrate 201, and 203 is an impurity diffusion layer formed on the surface of the semiconductor substrate 201.
．． 203a is an interlayer insulating film, 204 is a wiring electrode, 205 is amorphous silicon, and 206 is an upper electrode formed on the amorphous silicon 205. Note that the amorphous silicon 205 is a high resistance material, and the upper electrode 206
is made of a good conductor and is formed at the same time as the wiring electrode 204.

In the above configuration, the wiring electrode 204 and the amorphous silicon 205 are formed in contact with the surfaces of almost both ends of the impurity diffusion layer 202, and the amorphous silicon is formed between the upper electrode 206 and the lower electrode constituted by the impurity diffusion tank 202. 205 is inserted. In this structure, the high-resistance amorphous silicon 205 functions as the main component of the aforementioned antifuse. That is, the wiring electrode 204 connected to the upper electrode 206 and the lower electrode
When a voltage is applied between the two electrodes and a current is caused to flow, the portion centered on the amorphous silicon 205 between the two electrodes irreversibly transitions from a high resistance state to a low resistance state. In other words, a memory element can be configured by utilizing the fact that the portion centering on the amorphous silicon 205 between both electrodes changes from an insulating state to a conductive state, so that it can be distinguished from an element that does not conduct current.

[Problems to be Solved by the Invention] In the conventional semiconductor device as described above, in terms of device performance, it is desirable that the resistance value before transition R91 is higher and the resistance value R80 after transition is lower.

The R82 of amorphous silicon is somewhat lower than that of an insulating film such as an oxide film, and is not preferable. On the other hand, it has advantages and disadvantages, as it is superior in reliability compared to elements that use insulation film breakdown. Furthermore, in order to lower RQn, it is effective to include acceptor ions or donor ions in amorphous silicon;
The conventional element had an undesirable configuration because the current was low.

This invention was made in order to overcome the above-mentioned problems.
and R8. due to the inclusion of impurity ions. It is an object of the present invention to provide a semiconductor device having a structure that can take advantage of the effect of , reduction, and that does not have any adverse effect on other semiconductor devices on the same substrate, and a method for manufacturing the same.

[Means for Solving the Problems] A semiconductor device according to the present invention includes a semiconductor device that constitutes an untied fuse that transitions from a high resistance state to a low resistance state when a voltage is applied and a current flows. It has a four-layer structure consisting of a silicon insulating film and an upper electrode. There are two types of this four-layer structure: one in which a silicon insulating film, amorphous silicon, and an upper electrode are formed in this order from the impurity diffusion layer or polycrystalline silicon side of the lower electrode, and one in which amorphous silicon, a silicon insulating film, and an upper electrode are formed in this order. be. Further, the amorphous silicon used in the above two configurations may contain a group III or group V impurity element.

Further, in the method for manufacturing a semiconductor device according to the present invention, an interlayer insulating film is formed on a semiconductor substrate on which a lower electrode is formed, a contact hole for forming one electrode is formed, and a silicon oxide film is formed in this contact hole. and amorphous silicon by CVD method, thermal oxidation method or R2So
An upper electrode is formed on the amorphous silicon formed and patterned by the 4+H20□ process to form a four-layer structure electrode of a lower electrode silicon insulating film and an amorphous silicon upper electrode. Wiring electrodes are formed in contact holes. In addition, another method for manufacturing a semiconductor device according to the present invention includes forming a contact hole in the first contact hole.
First, amorphous silicon is deposited and a silicon insulating film is formed, and then a semiconductor element having a four-layer electrode structure consisting of an amorphous silicon lower electrode, a silicon insulating film, and an upper electrode is formed in the same manner as the above manufacturing method.

[Function 1] In this invention, the element that functions as an antifuse in the semiconductor element has a four-layer structure consisting of an upper electrode, amorphous silicon, a silicon insulating film, and a lower electrode. The film ensures high resistance, and the reliability of the antifuse is ensured by the properties of amorphous silicon. Since the silicon insulating film is used for the purpose of ensuring high Rore, it can be very thin, and by making it thin, it can be easily destroyed when a programming voltage is applied, so it has almost no effect on Ron. It is also easy to lower the resistance.

Also, in the amorphous silicon region in the four-layer structure, III
For those doped with group or V group impurities, when ion implantation is performed at about 1015 cm-3, part of the amorphous silicon melts due to Joule heat generated by the current generated by the application of the program (write) voltage. When that part cools, it probably changes into something like polycrystals.

At this time, the doped impurity element is incorporated into this crystal-like substance (this term is generally referred to as a filament in the academic and patent fields) and is activated, resulting in Ro. can be lowered.

[Example] Example 1 FIG. 1 is a structural explanatory diagram using a schematic cross-sectional view of a semiconductor element showing an example of the present invention. 101 is, for example, a silicon single crystal semiconductor substrate, 102 is an n" type or p4 type impurity diffusion layer (lower electrode), 103.103a is an interlayer insulating film, 104 is a wiring electrode such as Aff, 105 is amorphous silicon, 106 is an upper electrode such as A2, 107 is S
i A silicon insulating film formed of O2 or Si3N4,
108 is a contact hole. The upper electrode 106, the amorphous silicon 105, the silicon insulating film 107, and the lower electrode 102 form an electrode with a four-layer structure, which is the main component of the intact fuse. 2 is characterized in that a silicon insulating film 107 is interposed between the lower electrode 102 made of an impurity diffusion layer and the amorphous silicon 105, compared to the conventional example shown in FIG.

When the silicon insulating film 107 is interposed between the amorphous silicon 105 and the lower electrode (impurity diffusion layer) 102 as in the embodiment shown in FIG. A film is formed, and since this insulating film is amorphous,
Homogeneous amorphous silicon can be formed. Therefore, stability and reproducibility of programming voltage and current are improved.

This point is significantly greater than in the conventional example shown in Figure 2, where amorphous silicon is grown on a substrate, which makes it easier to grow abnormal growths that follow the silicon crystal, making it difficult to form homogeneous amorphous silicon. This can be said to represent a significant improvement. Note that the amorphous silicon 105 may be doped with a group III or group V impurity element of the same conductivity type as the impurity diffusion layer 102, and in this case, Ro should be lowered than when no impurity is doped. What you can do is as described above.

Embodiment 2: FIG. 3 is a structural explanatory diagram using a schematic cross-sectional view showing another embodiment of the semiconductor device according to the present invention. Components that are the same as or equivalent to those in the embodiment shown in FIG. 1 are given the same reference numerals and their explanations will be omitted.

In the embodiment of FIG. 3, amorphous silicon 10
5 and the upper electrode 106, a silicon insulating film 107 is interposed therebetween. In this case too, Example 1
Similarly to the amorphous silicon 105, group III or V
Ro by doubling the impurity elements of the group. may be lowered.

As in the embodiment of FIG. 3, amorphous silicon 105
If a silicon insulating film 107 is disposed between the upper electrode 106 and the upper electrode 106, for example, a barrier metal such as Tin may be used below the upper electrode 106 to prevent A° C. from penetrating if a via hole occurs there. Even A! Since there is little reaction between the silicon insulating film 107 and the silicon insulating film 107, there is an advantage that troubles such as a decrease in yield do not occur. In this respect, since amorphous silicon has a remarkable reaction with A.degree. C., the reaction proceeds even at about 300.degree. C., for example, when the above-mentioned barrier metal is not used.

As a result, short circuits may occur during device manufacturing, resulting in defects. Furthermore, even when a barrier metal is used, pinholes and the like occur, resulting in a decrease in yield, which has overcome the problem that occurred in the conventional example as shown in FIG. 2.

Embodiment 3: FIG. 4 is a structural explanatory diagram using a schematic cross-sectional view showing another embodiment of the semiconductor device according to the present invention.

In this example, 404 polycrystalline silicon is used as the lower electrode, and a 408 silicon oxide film and a 40
It has a four-layer structure of amorphous silicon (No. 5) and an upper electrode (No. 407). It is programmed by the Joule heat generated when a voltage is applied between the electrodes and a current is passed, but as in this example, polycrystalline silicon is used for the lower electrode,
By surrounding it with a silicon oxide film, the thermal conductivity can be lowered and the temperature rise due to Joule heat can be accelerated, allowing highly efficient programming.

Further, the silicon oxide film 408 may be present between the polycrystalline silicon 404 and the amorphous silicon 405, or may be formed between the amorphous silicon 405 and the amorphous silicon 405 other than in this embodiment.
05 and the upper electrode 407, or may exist on both sides of the amorphous silicon 405.

Embodiment 4: An embodiment of the method for manufacturing a semiconductor device according to the present invention will be described in (a) to 4 with reference to the semiconductor device shown in the embodiment of FIG.
The manufacturing steps in (f) will be explained in order.

Note that the step (C2) is an additional step when doping amorphous silicon with an impurity element. However, if doping is not necessary, this step is omitted.

(a) Process: Silicon (Sl) semiconductor substrate 101
An impurity diffusion layer 102 is formed on the entire surface, and 5i02 or S
After forming the i3N4 interlayer insulating film 103, a contact hole 108 is formed by photolithography at a predetermined location above the impurity diffusion layer 102 where amorphous silicon is to be deposited. (b) Process: S by CVD method
A silicon insulating film 107 is formed at the bottom of the contact hole 108 by depositing iO□ to a thickness of 100 Å or less, for example, by 50 people.

(C) Process: Amorphous silicon 105 is formed to a thickness of approximately 1,500 mm using the SVD method at 560° C., and is also embedded in the contact hole 108.

(C2) Step... When doping the amorphous silicon 105 with an impurity element, it is performed in this step. For example, if p (group V element) is used as the n-type impurity, p''' is doped with 60Ke
Ion implantation is performed under the conditions of y, l×10 15 to 1×10 16 cm −3 to dope p into the amorphous silicon 105 . In addition, as an n-type impurity, for example, in the case of B (Ill group element), BF2+ is 80Kev, 1×1015 to 1
Ion implantation is performed under the condition of x1016 cm-3 to dope B.

(d) Process: The amorphous silicon 105 is photoetched and patterned to form the amorphous silicon 105 in the shape of an electrode.

(e) Process: After depositing an interlayer insulating film 103a on the entire surface, a contact hole 108a for connecting the lead wiring
and 109 are formed. Contact hole 108a is formed to reach the top surface of amorphous silicon 105, and contact hole 109 is formed to reach the top surface of impurity diffusion layer 102.

(f) Process: First, a barrier metal such as Ti--TiN is deposited using a spack method, and then A° C.-81 is deposited using a spattering method, and patterning is performed to form the wiring electrode 104 and the upper electrode 106.

This completes the formation of the basic structure of the example element shown in FIG. In step (b), the SiO2 film is formed using, for example, N.
50 to 100 SiO□ films may be grown by thermal oxidation at 900° C. for 130 minutes in an atmosphere with a 02 concentration of 2% in two gases. In addition, as another method, H2SO4+H
It may be a 5in2 film grown in several tens of layers in 202 cm, or it may be annealed SiO2 at 900°C.

Embodiment 5: Another embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to the semiconductor device shown in the embodiment of FIG.
The steps in E) will be explained in order. Note that step (B2) is an additional step for doping amorphous silicon with an impurity element, but its contents are the same as step (C2) in Example 3, so its explanation will be omitted.

(A) Process: An impurity diffusion layer 1.02 is formed on a silicon semiconductor substrate 101, and 5in2 or 5IN4 is formed on the entire surface.
After forming the interlayer insulating film 103, the impurity diffusion layer 10 is formed.
A contact hole 1 is formed using photolithography technology at a predetermined location where amorphous silicon 105 is planned to be formed above 2.
08 is formed.

(B) Process: An amorphous silicon (film) 105 is formed to a thickness of about 1500 mm using the CVD method at 560° C., and is also embedded in the contact hole 108.

(B2) Step... Example 3 when doping group III or group V impurities into amorphous silicon 105
P or B is doped by ion implantation in the same manner as in step (C2).

(C) Step: The amorphous silicon (film) 105 is etched by dry etching using CF4 to form the amorphous silicon 105 in the shape of an electrode.

(D) Process: After depositing the interlayer insulating film 103a on the entire surface, the contact hole 1.08 for connecting the lead wiring
a and 109 are formed.

(E) Step: A 5in2 (film) 107 is formed to a thickness of about 100 layers or less using the CVD method.

Amorphous silicon (film) 10 by photoetching
5iOz (film) 107 other than on 5 is removed.

(F) Step: The wiring electrode 104 and the upper electrode 106 are formed in the same manner as the step (f) of Example 3, and the process up to this stage is completed.

Note that the semiconductor device according to the present invention is not only effective for use as an unquenchable device, but also for use in the above-mentioned PLA.
It can be applied to a semiconductor device formed by incorporating it into a general storage device or a general memory device. Further, as described above, it can be used directly as a FROM element, or as a wiring connection switch for other devices. In other words, one application of the wiring connection switch is that by inserting it into the wiring connection point of an IC such as a macro cell such as a standard cell for a specific purpose, it has the advantage of allowing the user to create any IC on the desktop. .

[Effects of the Invention] As described above, according to the present invention, in addition to using conventional amorphous silicon for the part used as an untie fuse of a semiconductor element, by arranging an insulating film above or below it, the program element can be Since it consists of
art is ensured by a silicon insulating film, and reliability is ensured by amorphous silicon. Therefore, the synergistic effect of the above two effects improves the stability and reproducibility of the program current/voltage during operation. Therefore, high Ra
te and Ro lower than before. A program element with characteristics is obtained.

Furthermore, according to this structure, even if amorphous silicon is doped with impurities to lower Ron, there is no effect on R02 (high R0te and low R0° characteristics can be achieved.Especially when the structure shown in Fig. 3 In this case, the upper electrode material itself,
Since the reaction between a part of the amorphous silicon, such as a barrier metal, can be prevented, the manufacturing process becomes easier.

From the above, it becomes easy to form an untie fuse and apply it to a PLA or a memory device to be incorporated, which contributes to lowering the overall cost.

Furthermore, the present invention uses polycrystalline silicon or the like formed above the semiconductor substrate instead of a diffusion region formed in the semiconductor substrate for the lower electrode, and furthermore, an oxide film is formed between the polycrystalline silicon and the amorphous silicon or between the amorphous silicon and the upper part. If it is provided between the electrodes or both, the following effects can be obtained in addition to the above-mentioned effects.

In other words, when the oxide film is formed from a thermal oxide film, the thermal influence on the semiconductor substrate can be reduced, and the redistribution of impurities in the diffusion region of the substrate that constitutes the semiconductor element can be suppressed, improving reliability. This has the effect that a semiconductor device with high performance can be obtained.

Furthermore, the following effects can be obtained by using polycrystalline silicon provided on the substrate with an insulating film in between instead of the impurity layer formed on the substrate for the lower electrode.

1. The oxidation rate on polycrystalline silicon is faster than that on single-crystalline silicon, so it can be processed at low temperatures for a short time, and the effect on the characteristics of the underlying transistor can be reduced.

2. An oxide film grown on polycrystalline silicon has a lower breakdown voltage than a film grown on single-crystalline silicon, making it possible to reduce the increase in programming voltage.

3. Oxide films grown on polycrystalline silicon have poorer crystallinity than films grown on single-crystal silicon, and are effective against amorphous silicon films. If the crystallinity is good, amorphous silicon may become polycrystalline at the interface with the oxide film.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of essential parts showing one embodiment of a semiconductor device of the present invention, FIG. 2 is a cross-sectional explanatory diagram showing the structure of a conventional semiconductor device, and FIG. FIG. FIG. 4 is a sectional view of a main part showing another embodiment of the present invention. In the figure, 109...Contact pole 401...
...Silicon substrate 402,403...Insulating film 408...Silicon oxide insulating film 405...
...Amorphous silicon 407...Top electrode and above Applicant Seiko Epson Co., Ltd. Agent Patent attorney Kizobe Suzuki (1 other person) 101,
102 ・ ・ 102, 202 ・ ・ 103, 103a- 104, 204 ・ ・ 105 , 205 ・ ・ 106, 206 ・ ・ 107 ・ 108, 108a ・Silicon semiconductor substrate, impurity diffusion layer, interlayer insulating film, wiring electrode, amorphous Silicon, upper electrode, silicon insulation film, contact hole

Claims (6)

[Claims] (1) By applying a voltage between the electrodes formed on the surface of the semiconductor substrate and causing a current to flow, the state between one of the electrodes and the other of the electrodes is changed from a high resistance state to a low resistance state. A semiconductor device comprising a four-layer structure including an upper electrode, amorphous silicon, a silicon oxide insulating film, and a lower electrode. (2) The semiconductor device according to claim 1, wherein the one electrode comprises an impurity diffusion layer formed on the surface of the semiconductor substrate. (3) The semiconductor device according to claim 1, wherein the one electrode is made of polycrystalline silicon. (4) The semiconductor device according to any one of claims 1 to 3, wherein the amorphous silicon contains a group III or group V impurity element. (5) A semiconductor element that causes a transition from a high resistance state to a low resistance state between one of the electrodes and the other electrode by applying a voltage between the electrodes formed on a semiconductor substrate and causing a current to flow therebetween. In the manufacturing method, a step of forming an interlayer insulating film on the semiconductor substrate on which the lower electrode is formed, a step of forming a contact hole in the interlayer insulating film, and a CVD method, a thermal oxidation method, or a H_2SO_4+H_2O_2 treatment on the bottom of the contact hole. After forming a silicon insulating film, amorphous silicon is deposited on the entire surface, and a layer of amorphous silicon is patterned on the silicon oxide film by photo-etching.After forming an interlayer insulating film, a layer of amorphous silicon is formed on the amorphous silicon and another layer. The method is characterized by comprising a step of forming a contact hole for an electrode lead-out wiring, and a step of forming an upper electrode and the other electrode lead-out wiring on the amorphous silicon by vapor-depositing an electrode material over the entire surface and patterning it. A method for manufacturing semiconductor devices. (6) A semiconductor element that transitions from a high resistance state to a low resistance state between one electrode and the other electrode by applying a voltage between the electrodes formed on a semiconductor substrate and causing a current to flow. In the manufacturing method, a step of forming an interlayer insulating film on the semiconductor substrate on which the lower electrode is formed, a step of forming a contact hole in the interlayer insulating film, depositing amorphous silicon that reaches the bottom of the contact hole, and photoetching the A step of patterning a layer of amorphous silicon, a step of forming an interlayer insulating film and then forming contact holes for drawing out two electrodes, a step of forming a silicon insulating film by a CVD method, and a silicon insulating film on the amorphous silicon layer. the process of forming;
A method for manufacturing a semiconductor device, comprising: