JPH02146834U - - Google Patents
Info
- Publication number
- JPH02146834U JPH02146834U JP1989053612U JP5361289U JPH02146834U JP H02146834 U JPH02146834 U JP H02146834U JP 1989053612 U JP1989053612 U JP 1989053612U JP 5361289 U JP5361289 U JP 5361289U JP H02146834 U JPH02146834 U JP H02146834U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- semiconductor
- mounting board
- connection structure
- connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
- H10W72/07554—Controlling the environment, e.g. atmosphere composition or temperature changes in dispositions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/547—Dispositions of multiple bond wires
Landscapes
- Wire Bonding (AREA)
Description
第１図は、本考案の半導体装置の接続構造の一
実施例を示す主要平面図。第２図は、第１図の主
要断面図。第３図は、従来の半導体装置の接続構
造を示す主要平面図。第４図は、第３図の主要断
面図。
１……半導体装置、２……半導体装置の接続端
子、３，４……半導体装置取付基板上の接続端子
配置面、５……半導体装置取付基板上の接続端子
、６……ボンデイングワイヤー、７……半導体装
置取付基板。
FIG. 1 is a main plan view showing an embodiment of a connection structure for a semiconductor device of the present invention. FIG. 2 is a main sectional view of FIG. 1. FIG. 3 is a main plan view showing the connection structure of a conventional semiconductor device. FIG. 4 is a main sectional view of FIG. 3. DESCRIPTION OF SYMBOLS 1... Semiconductor device, 2... Connection terminal of semiconductor device, 3, 4... Connection terminal arrangement surface on semiconductor device mounting board, 5... Connection terminal on semiconductor device mounting board, 6... Bonding wire, 7 ...Semiconductor device mounting board.
Claims (1)
体取付基板とを電気接続する半導体装置の接続構
造において、前記半導体取付基板の電気接続端子
が、高さの異なる複数の接続面に配されている事
を特徴とする、半導体装置の接続構造。 A semiconductor device connection structure for electrically connecting a semiconductor device and a semiconductor mounting board by wire bonding, characterized in that electrical connection terminals of the semiconductor mounting board are arranged on a plurality of connection surfaces having different heights. Connection structure of semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989053612U JPH02146834U (en) | 1989-05-10 | 1989-05-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989053612U JPH02146834U (en) | 1989-05-10 | 1989-05-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02146834U true JPH02146834U (en) | 1990-12-13 |
Family
ID=31574951
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989053612U Pending JPH02146834U (en) | 1989-05-10 | 1989-05-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02146834U (en) |
-
1989
- 1989-05-10 JP JP1989053612U patent/JPH02146834U/ja active Pending