JPH0214733B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] Directly decodes instructions read from memory, sets them in the instruction register through an ECC circuit in parallel, and executes instructions based on the directly decoded contents if there is no error. In an instruction processing device configured to execute the instruction by decoding the corrected instruction in the instruction register using the ECC circuit and executing the instruction if an error exists, the instruction processing device inputs/outputs the input/output to other devices using a common bus. When attempting to issue an instruction, if the relevant input/output instruction cannot be executed due to reasons such as the common bus being busy, the same input/output instruction set in the instruction register is decoded and executed without re-reading the instruction from memory. It is something to do.

[Industrial application field]

The present invention provides an instruction processing device in a data processing device configured such that an instruction processing device and other devices are connected by a common bus, and the instruction processing device uses input/output instructions when exchanging information with the other devices. This is related to the instruction execution method.

[Conventional technology]

In conventional instruction processing devices, when an input/output instruction that uses a common bus cannot be executed because it cannot acquire the common bus due to conflict with the cycle steal operation of another device, this instruction execution sequence is cleared and the cycle of the other device is After the steal operation, the same input/output instruction is read out from memory, decoded, and executed again.

[Problem that the invention seeks to solve]

According to the above method, there is a drawback that the instruction processing capacity is reduced by the time it takes to read the instructions from the memory again.

[Means for solving problems]

According to the present invention, when an input/output instruction that uses a common bus cannot be executed because the common bus cannot be acquired, the memory does not read the input/output instruction again.
The same input/output instruction held in the instruction register via the ECC circuit is used to decode and re-execute the same input/output instruction.

[Effect]

The present invention provides an instruction processing device having an ECC circuit, in order to achieve high-speed processing, instructions read from memory are normally decoded directly and executed, and only when an error occurs, the corrected instruction is executed by the ECC circuit. When an input/output instruction that uses a common bus cannot be executed because the common bus cannot be acquired, the same input/output instruction is executed based on the contents of the instruction register that holds the output of the ECC circuit. That's what I do. Therefore, there is no need to read instructions from the memory again, and the instruction processing capacity can be improved.

〔Example〕

FIG. 2 is a diagram showing a block configuration of a communication control device according to an embodiment to which the present invention is applied.

In the figure, 20 is a central control unit (CCU) which is an instruction processing unit, 21 is a memory, 22 is a line control unit, 2
3 is a channel adapter (CA), 24 is a line support section, and 25 is a common bus.

Here, the central control unit 20 is a command processing device that executes a control program stored in a memory 21, and the channel adapter 23 and line control unit 22 are controlled by input/output commands from the central control unit 20, and are controlled by cycle stealing. Data is transferred to and from the memory 21.

FIG. 1 is a block diagram showing the internal configuration of the central control unit of the embodiment, and in the figure, 1 is a memory (MS).
2 is memory read data register (MRDR), 3 is
ECC circuit, 4 is instruction register (IR), 5 is instruction decode circuit, 6 is sequence control circuit, 7 is bus control circuit, 8 is arithmetic circuit (ALU), 9 is work register, 10 is memory address register (SAR) ,
11 is the instruction address register (IAR), 12 is the memory write data register (MWDR), and 13 is the instruction address register (IAR).
ECC circuit 14 is a common bus.

The operation of FIG. 1 is as follows.

Data read from MSI is set in MRDR2.

The output data of MRDR2 is sent to the instruction decode circuit 5.
At the same time, ECC circuit 3 decodes 1
Bit errors are automatically corrected and retained in IR4.

If a 1-bit error occurs at this time, the above
The decoding by the output data of MRDR2 is disabled, and the output data of IR4 is decoded by the instruction decoding circuit 5.

As a result of decoding, the instruction is executed under the control of the sequence control circuit 6.

When the instruction is an input/output instruction that uses a common bus, the sequence control circuit 6 notifies the bus control circuit 7, and the bus control circuit 7 attempts to acquire the bus. If so, the bus control circuit 7 notifies the sequence control circuit 6.

The sequence control circuit 6 disables control of this input/output instruction and controls cycle stealing.
When the cycle steal is completed, since the input/output instruction that could not be executed is held in the IR4, the output data of the IR4 is decoded by the instruction decoding circuit 5 and executed.

〔Effect of the invention〕

According to the present invention, the number of memory accesses for reading instructions is reduced, so that instruction processing capacity is improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the internal configuration of a central control unit according to an embodiment, and FIG. 2 is a diagram showing a block configuration of a communication control device according to an embodiment to which the present invention is applied. In Figure 1, 1 is a memory, 3 is an ECC circuit,
4 is an instruction register, 5 is an instruction decode circuit, 6 is a sequence control circuit, 7 is a bus control circuit, and 14 is a common bus.

Claims (1)

[Scope of Claims] 1. Means for decoding an instruction read from a memory without performing automatic error correction by the error check and correction circuit, and means for holding in an instruction register the instruction whose error has been automatically corrected by the error check and correction circuit. An instruction processing device having means for decoding the instructions held in the instruction register again when an error occurs, and is connected to other devices via a common bus, and has an input/receiver that uses the common bus to exchange information with other devices. In an instruction processing device that executes an output instruction, when an input/output instruction that uses the common bus cannot be executed because the common bus cannot be acquired, the input/output instruction is not read out from memory again and the input/output instruction is stored in the instruction register. An instruction processing device characterized in that the instruction processing device is configured to re-execute the input/output instruction using means for decoding the instruction held in the instruction.