JPH02148149A - Memory system - Google Patents

Abstract

PURPOSE:To constitute a memory system in a narrow space by sharing a buffer between a cache memory and a main memory. CONSTITUTION:When a control signal and an address 8 are sent from a CPU 1 for the purpose of reading a memory, a hit discriminating mechanism 6 discriminates whether a cache memory 4 is hit for this address or not, and a memory control part 5 decides the access to a main memory 3 or that to the cache in accordance with the discrimination result and selects the memory control of the main memory or the cache. The main memory 3 or the cache memory 4 from which data should be received by a memory buffer 2 is indicated. Data read out from the memory is inputted to a data bus 7 through the shared memory buffer 2. Since the buffer 2 is shared between the cache memory and the main memory, the memory system of narrow space is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory system equipped with a cache memory.

[Conventional technology]

With the remarkable progress of office automation in recent years, there has been a desire for high-speed, large-capacity, inexpensive, and small-space memory systems. Therefore, cache memory that effectively uses static RAM as part of the memory, which is fast but requires a considerable amount of space, has recently begun to be used.

A conventional memory system of this type, as shown in FIG.
Cache memory 15 composed of static RAM
Two buffers are used: a cache buffer 13 that stores data read from the cache when a hit occurs, and a main memory buffer 12 that stores data read from the main memory 14 when a miss occurs. By controlling the cache control unit 17 and the main memory control unit 16, the CPU II sees the same data as data read from memory.

[Problem to be solved by the invention]

In the conventional memory system mentioned above, there are two types of buffers, one for cache memory and one for main memory, so even if the main memory is a memory that is a little slow but takes up a small space, it is not easy to make it lighter, thinner, and smaller. There was a drawback that the brakes would apply. Recently, bus widths have tended to increase in order to improve performance, so two types of buffers are becoming more and more wasteful.

[Means to solve the problem]

A memory system of the present invention is a memory system equipped with a cache memory, and includes: a memory buffer that is used both as the cache memory and the main memory; and a human judgment that determines whether accessed data is registered in the cache memory. and a memory control unit that activates either the cache memory or the main memory according to the result of the determination, and causes the memory buffer to function in response to the activation. .

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention, in which the CPU
I. Memory buffer 2. Main memory 3゜Cache memory 4. It consists of a memory control section 5 and a hit determination mechanism 6.

When a control signal and an address 8 are sent from the CPU 1 to read the memory, the hit determination mechanism 6 determines whether or not the cache memory 4 has hit the address.

The memory control unit 5 determines whether to access the main memory 3 or the cache based on the result of this determination, and separates the memory control for each. It also instructs which of the main memory 3 and cache memory 4 the memory buffer 2 should accept data into. Data read from the memory passes through the dual-purpose memory buffer 2 and enters the data bus 7.

Note that even this memory buffer 3 is not necessary if output from the memory is guaranteed while the CPU 1 is reading.

〔Effect of the invention〕

As explained above, the present invention has a configuration in which a cache buffer and a main memory buffer are shared, and therefore has the advantage that a memory system can be constructed with a small space.

7 Day 9 no\'s

[Brief explanation of the drawing]

FIG. 1 shows a block diagram of an embodiment of the present invention, and FIG. 2 shows a conventional block diagram. 1.11...CPU section, 2...Buffer, 3,14
...Main memory, 4,15...Cache memory, 5
...Memory control unit, 7,19...Data bus, 7,
19... Data bus, 8... Control signal and address, 12... Main memory buffer, 13... Cache buffer, 16... Main memory control unit, 17...
- Cache control unit, 6.18... hit determination mechanism. Man 1 field

Claims (1)

[Scope of Claims] A memory system equipped with a cache memory, comprising: a memory buffer that serves as both the cache memory and main memory; and a hit determination mechanism that determines whether accessed data is registered in the cache memory. and a memory control unit that activates either the cache memory or the main memory according to the result of the determination, and causes the memory buffer to function in response to the activation. system.