JPH02148152A - Microcomputer - Google Patents

Abstract

PURPOSE:To prevent the third person from decoding internal secret information by disconnecting a ROM from a data bus by a data bus buffer at the time of program execution of an external circuit or the like. CONSTITUTION:While an external circuit 6 executes a program, a ROM output invalidating signal is outputted from a ROM output validating circuit 7 to a data bus buffer 8, and the data bus buffer 8 disconnects a ROM 3 from a data bus DB by this signal. As the result, the program in the ROM 3 cannot be read out by the external circuit 6. Thus, secret of the program in the ROM 3 is protected.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention provides a CPU, a ROM and a RAM each connected to the CPU via an address bus and a data bus, and a The microcomputer is connected via an address bus and has an address decoder that outputs a selection signal for selecting between the ROM and the RAM, and more specifically, the address decoder is connected to the ROM and the RAM, and is written in the ROM built in the microcomputer. This relates to preventing programs from being read from outside.

(Prior Art) FIG. 2 is a circuit configuration diagram of a microcomputer having a ROM as a read-only memory in which an old program is stored, and an external circuit connected to the microcomputer.

In FIG. 2, l is a microcomputer,
This microcomputer 1 includes a CPU 2, a ROM 3 in which a program defining the operation of the CPU 2 is written as a program memory for the CPU 2, and a ROM 3 that serves as a program memory for the CPU 2.
It is composed of a RAM 4 as a working memory of U2, and an address decoder 5 that outputs a selection signal for selecting either ROM 3 or RAM 4.

Therefore, ROM3 and RAM4 are connected to CPU2 via address bus AB and data bus DB, respectively.
Further, the address decoder 5 is connected to the CPLJ2 via the address bus AB, and the address decoder 5 is connected to the ROM.
3 and RAM 4 via selection signal lines SL.

An external circuit 6 is connected to the address bus AB and data bus DB of the microcomputer 1 having such a configuration.

In operation, as is well known, the CPU 2 built into the microcomputer 1 operates according to the program written in the ROM 3, and
The RAM 4 is used as a working memory for the CPU 2 when executing the program, and the external circuit 6 is used to execute various functions lacking in the microcomputer 1, such as a human output board and an external memory.

(Problem to be Solved by the Invention) In the above configuration, the data bus DB and the address bus A
Since r(0M3 and external circuit 6 are connected through The program contents are structured so that they can be freely read and decoded.Therefore, the above configuration has the disadvantage that it is difficult to keep the program contents of the ROM 3 confidential from a third party.

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to make it possible to keep the program contents of a ROM of a microcomputer confidential.

(Means for Solving the Problems) In order to achieve such an object, the microcomputer of the present invention includes a CPU, each of which has a
The ROM and RAM are connected to the CPU U via an address bus and a data bus, and the CPU is connected to the CPU U via an address bus, and the R
In a microcomputer having an address decoder that outputs a selection signal for selecting between OM and RAM, when an instruction fetch signal is input from the CPU and a selection signal for selecting the ROM is manually input from the address decoder, the ROM is output. RO that outputs a valid signal and a ROM output invalid signal at other times.
an M output enabling circuit connected between the data bus and the ROM, the R
A data bus buffer that connects the ROM to the data bus when an OM output valid signal is applied and disconnects the ROM from the data bus when the ROM output invalid signal is applied. It is said that

(Function) In the above configuration, the ROM output enabling circuit outputs the C
When an instruction fetch signal is input from the PU and a selection signal for selecting the program memory is input from the address decoder, a ROM output valid signal is output, and at other times, a ROM output invalid signal is output.

When the data bus buffer receives the ROM output enable signal from the ROM output enable circuit, the data bus buffer
M is connected to the data bus, and when the ROM output invalidation signal is applied, the rtOM is disconnected from the data bus.

Therefore, even if an external circuit connected to the CPU and the ROM via an address bus and a data bus attempts to read out the program in the ROM according to the program written therein, in this case, the Since the ROM is separated from the data bus by the data bus buffer which operates in response to the ROM output invalidation signal, the program in the ROM cannot be read out, and as a result, the I' (the secret of the OM program) cannot be read. It becomes possible to protect the

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit diagram of a microcomputer according to an embodiment of the present invention and an external circuit connected thereto;
The same reference numerals are given to the parts that are the same as or corresponding to those of the conventional example shown in the drawings, and detailed explanations of the parts corresponding to the same reference numerals will be omitted except for listing their names.

That is, in FIG. 1, 2 is a microcomputer, 2 is a CPU, 3 is a ROM 14, a RAM 15 is an address decoder, 6 is an external circuit, AB is an address bus, DB is a data bus, and SL is a selection signal line.

The configuration of this embodiment differs from the conventional example as follows.

That is, in this embodiment, an instruction fetch signal is manually input from the CPU 2 to the microcomputer 1 via the signal line SLI, and a selection signal for selecting the ROM 3 is input from the address decoder 5 via the signal line SL2. A ROM output enabling circuit 7, which outputs a ROM output enable signal at times and a ROM output disable signal at other times, is connected between the data bus DB and the ROM3, and the ROM output from the ROM output enable circuit 7 is connected between the data bus DB and the ROM3. When a valid signal is given, ROM3 is transferred to data bus DB.
The data bus buffer 8 is connected to the data bus DB and operates to disconnect the ROM 3 from the data bus DB when the ROM output invalidation signal is applied.

Therefore, according to the microcomputer of this embodiment having the above configuration, the selection signal for selecting the ROM 3 from the address decoder 5 to the ROM output enabling circuit 7 is
Further, when each instruction fetch signal is input from the CPU 2, the data bus buffer 8 operates in response to the ROM output enable signal from the ROM output enable circuit 7, and the RO
Since M3 is connected to the data bus DB, the CPU 2 can execute the operation JIN[f based on the program in the ROM3. Also, while the external circuit 6 is executing a program, the data bus buffer 8 is
A ROM output invalidation signal is output to the data bus DB, whereby the data bus buffer 8 disconnects the ROM 3 from the data bus DB. As a result, using the external circuit 6, FtOM
Program 3 cannot be read.

In this embodiment, only the reading of the program from the ROM 3 is restricted, but it is also possible to prohibit the reading and writing of other memories, human output boards, etc. in the same way.

(Effects of the Invention) As is clear from the above explanation, according to the present invention,
When an external circuit is executing a program, the ROM and data bus are separated by the data bus buffer, so the program in the ROM cannot be read by the external circuit, and as a result, a third party can read the program from the ROM. It is possible to effectively prevent decoding of internal confidential information of a computer.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a microcomputer according to an embodiment of the present invention and an external circuit connected thereto, No. 25! J
1 is a circuit diagram of a conventional example corresponding to FIG. ■...Microcomputer, 2...CPU, 3R
OM, 4...RAM, 5...Address decoder, 6
...External circuit, 7...ROM output enable circuit, 8...
Data bus buffer, DB...Data bus, AB...
Data bus, SL-...Selection signal line, SLI, SL2
Signal line. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] (1) a CPU, a ROM and a RAM each connected to the CPU via an address bus and a data bus; and a ROM and a RAM connected to the CPU via an address bus; In a microcomputer having an address decoder that outputs a selection signal for selecting the RAM, when an instruction fetch signal is input from the CPU and a selection signal for selecting the ROM is input from the address decoder, a ROM output valid signal is output. and R outputs a ROM output invalid signal at other times.
an OM output enabling circuit connected between the data bus and the ROM to connect the ROM to the data bus when the ROM output enable signal is applied from the ROM output enabling circuit; When the output invalidation signal is given, the R
A microcomputer comprising: a data bus buffer that operates to disconnect an OM from the data bus.