JPH02148236A - Storage device - Google Patents

Abstract

PURPOSE:To execute the memory management of one address unit at a high speed without using a program by constituting a free memory list of a head free memory address register and a next free memory address register. CONSTITUTION:Each address of a data memory 1 constitutes the data memory 1 and a next free memory address memory 8 so that one address each of the next free memory address register 8 corresponds. In a head free memory address register 7, an address 1a of a data memory being a head free memory is stored, and in an address 8a of the next free memory address memory indicated by its contents, an address of a data word unit of the next free memory, namely, an address 8b of the next free memory address memory is stored. Also, in the address 8b of the next free memory address memory, an address of a data word unit of the next free memory thereof is stored. In such a way, the memory management of one address unit can be executed at a high speed without using a program.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a storage device used in a data processing device, and particularly to memory allocation/release.

[Prior Art] FIG. 3 is a block diagram showing a conventional storage device. In the figure, (1) is a data memory, (2) is an address bus that provides an address from a data processing device (not shown) to the data memory (1), and (3) is a connection between the data processing device and the data memory (1). (4) is the control circuit, (5) is the data bus for transferring read/write data between
is a command signal line from which the data processing device gives read/write commands to the control circuit (4), and (6) is a control signal that the control circuit (4) generates in response to commands from the command signal line (5) to the data memory <1. ) is a control signal line that transmits to the

A conventional storage device is configured as described above, and this storage bag π
To read data from , follow the steps below.

(2) The data processing device outputs the address of the memory to be read to the address bus (2), and also gives a read command to the control signal line (5).

■ The control circuit (4) decodes the read command from the command signal line (5) and transfers it to the data memory (1) from the control signal line (6).
gives control signals to read the memory through.

(2) The data memory (1) reads the contents of the memory at the address output to the address bus (2) according to the control signal line of the control signal ti (6), and outputs it to the data bus (3).

Also, when writing data to this storage device, follow the steps below.

(2) The data processing device outputs the memory address to be written to the address bus (2) and the data to be written to the data bus (3), and also gives a write command to the command signal line (5).

(2) The control circuit (4) decodes the write command on the command signal line (5) and provides a control signal for writing to the data memory (1) via the control signal line (6).

(2) The data memory (1) writes the data output to the data bus (3) to the address output to the address bus (2) according to the control signal on the control signal line (6).

Using this storage device, we will consider implementing memory management in units of locations for effective memory utilization. What is this memory management in units of locations? It is allocated or released when a program is executed. This is a function in which the unit of memory is the first location, and is necessary to implement a language processing system for languages such as Pro log and LISP, which set values to variables and release variables at the time of program execution. In order to realize memory management in units of first location using this storage device, a program is required, and the implementation method using two typical programs will be described below.

(a) Memory availability is managed using a bit table (the first location in memory corresponds to one bit). That is, when allocating memory, sometimes a free address is searched from this bit table, and when allocated memory is released, a bit in the bit table corresponding to the address is set to free.

(b) Manage a list of free memory addresses.

Memory allocation sometimes takes the first element from the free memory list and allocates it, and when memory is released, the freed memory is added to the free memory list.

Either way, you must implement a program that has this kind of functionality.

[Problems to be Solved by the Invention] In the conventional storage device as described above, a program is required to realize memory management in units of locations, and it takes time and effort to implement this program. Therefore, there is a problem in that it takes time to allocate/release memory.

This invention was made to solve this problem, and provides a storage device that can perform memory allocation/release at high speed without requiring a program to realize memory management in units of locations. The purpose is to

[Means for Solving the Problems] A storage device according to the present invention has seven first free memory address registers for storing the address of the first free memory and a next free memory for storing the address of the first free memory. an address memory; a read/write means for reading/writing the contents of the first free memory address register as an address of the data memory and the next free memory address memory; and the read/write means. storage means for storing the contents of the next free memory address memory means read out by the above into the first free memory address register; and storage means for storing the contents of the first free memory address register into the next free memory address register. It is provided with a write means for writing, and a storage means for storing the contents of the data outputted to the address bus in the first free memory address register.

[Operation] In the present invention, a free memory list is constructed from a first free memory address register and a next free memory address register, and this free memory list is used to realize memory management in units of locations.

[Embodiment] FIG. 1 is a block diagram showing a storage device according to an embodiment of the present invention. In FIG. 0, (1) to (6) are the same as the conventional one. (7) is the first free memory address register for storing the address of the first free memory, (8) is the next free memory address register for storing the address of the next free memory, and (9) is the first free memory address register. Free memory address register (7) and next free memory address
A free memory address bus (10) transfers free memory addresses between the address bus (2) and the first free memory address register (7). (11) is a control signal line (12) for transmitting a control signal generated by the control circuit (4) in response to a command from the command signal line (5) to the first free memory address register (7). )
The control circuit (4) receives the command from the command signal line (5) and sends the control signal to the next free memory address memory (8).
This is a control signal line for transmitting signals to the Note that the address bus (2) transfers addresses between the data processing device (not shown), the data memory (1), and the next free memory address memory (8).

FIG. 2 shows a diagram for explaining the invention in detail.

In a storage device configured as described above.

First, a free memory list is constructed from the first free memory address register (7) and the next free memory address register (8), and the second method uses this free memory list to realize memory management by location. This will be explained using figures.

Figure 2 (a) shows the free memory list, pig memory (
Each address in 1) has the next free memory address register (8
), the data memory (1) and the next free memory address memory (8) are configured so that they correspond to each other. For example, in FIG. 2(a), address (1) of the data memory
a) contains the next free memory address memory address (8
The data memory address (1b) in a) corresponds to the next free memory address memory address (8b).

The first free memory address register (7) stores the address (1a) of the data memory, which is the first free memory, and the next free memory address (8a) pointed to by its contents is the address of the first free memory. An address in data word units, that is, the next free memory address memory address (8b) is stored. Furthermore, the address of the next free memory in data word units is stored in the address (8b) of the primary free memory address memory.

A list in which all free memories are connected in the form of a chain is called a free memory list.

In memory allocation using this free memory list,
From the state of FIG. 2(a), the data memory address (la
), next free memory address/memory address (8a)
The bare memory is removed from the free memory list and allocated as new memory, resulting in the state shown in FIG. 3(b). This is executed by moving the contents of the address (8a) of the primary free memory address memory to the first free memory address register (7).

Conversely, when releasing memory, the state shown in Fig. 3(b) changes to the state shown in Fig. 3(a>) when the bare addresses (1a>, (8a) to be released are connected to the free memory list I. sets the contents of the first free memory address register (7) to 1
This is executed by moving to the next free memory address memory address (8a) and further setting the data memory address (1a) to the first free memory address register (7).

Now, in the storage device shown in FIG. 1, allocating a new memory and writing data to that memory is performed in the following steps.

(2) The data processing device outputs the data to be written to the data bus (3), and also gives instructions for memory allocation and writing to the command signal line (5).

■ The control circuit (4) decodes the memory allocation and write commands on the command signal line (5), outputs the contents of the first free memory address register (7) to the address bus (2), and also outputs the contents of the first free memory address register (7) to the address bus (2). ) to the control signal line (6
) to the control signal line (12) to the primary free memory address memory (8).
) gives a control signal to read the memory.

(2) The data memory (1) writes the contents of the data output to the data bus (3) to the address output to the address bus (2) in accordance with the control signal on the control signal line (6).

(2) The next free memory address memory (8) reads the memory contents at the address output to the address bus (2) in accordance with the control signal on the control signal line (12), and outputs it to the free memory address bus (9).

■ Next, the control circuit <4)
A control signal for setting the register (7) is applied to the register (7) via a control signal line (11).

■ The start free memory address register (7) sets the contents of the data output to the free memory address bus <9) as a new start free memory address in this register (7) according to the control signal of the control signal line (11). do.

In this storage device, memory is released in the following steps.

(2) The data processing device outputs the address of the memory to be released to the address bus (2), and also gives a memory release command to the command signal line (5).

■ The control circuit (4) decodes the memory release command on the command signal line (5>) and stores the first free memory address register (7).
) is output to the free memory address bus (9), and a control signal for writing to the primary free memory address memory (8) is given via the control signal line (12).

(2) The next free memory address memory (8) writes the contents of the data output to the free memory address bus (9) to the address output to the address bus (2) in accordance with the control signal on the control signal line (12).

■ Next, the control circuit (4)
A control signal for setting the register (7) is applied to the register (7) via the control signal line (11).

■ The start free memory address register (7) sets the contents of the data output to the 2-address bus (2) as a new start free memory address in accordance with the control signal of the control signal line (1)). .

[Effects of the Invention] As explained above, the present invention includes a first free memory address register for storing the address of the first free memory and a next free memory address register for storing the address of the first free memory. and the contents of the first free memory address register as the address of the data memory and the next free memory address register for reading/writing the respective memories.
a writing means, a storage means for storing the contents of the next free memory address memory read by the reading/writing means in the first free memory address register, and a storage means for storing the contents of the next free memory address register read by the read/write means; Since it is equipped with a writing means for writing to the next free memory address register and a storage means for storing the contents of the data output to the address bus in the first free memory address register, - memory in address units. This has the effect of providing a storage device that can be managed at high speed without using a program.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a storage device according to an embodiment of the present invention, FIG. 2 is an operation explanatory diagram for explaining the present invention in detail, and FIG. 3 is a block diagram showing a conventional storage device. In the figure, (1) data memory, (2) address bus, (3) data bus, (4) control circuit,
(7>...Start free memory address register, (8)
. . . Next free memory address memory, (9) . . . Free memory address bus, (10) Address transfer path. Note that the same reference numerals in each figure indicate the same or equivalent parts. i2 Figure 7, (b) Field 2 - Atoshi Suba input, 12 - Control signal medium

Claims (1)

[Claims] A first free memory address register for storing the address of the first free memory, a next free memory address memory for storing the address of the next free memory, and the contents of the first free memory address register are stored as data. a read/write means for reading/writing each memory as a memory and the next free memory address/memory address;
The content of the next free memory address/memory read by the writing means is written to the first free memory address/memory.
storage means for storing the contents of the first free memory address register into the next free memory address register; and writing means for writing the contents of the first free memory address register into the next free memory address register; - A storage device characterized by comprising: storage means for storing data in a register.