JPH02148751A - Pad layout for semiconductor device - Google Patents
Pad layout for semiconductor deviceInfo
- Publication number
- JPH02148751A JPH02148751A JP30182688A JP30182688A JPH02148751A JP H02148751 A JPH02148751 A JP H02148751A JP 30182688 A JP30182688 A JP 30182688A JP 30182688 A JP30182688 A JP 30182688A JP H02148751 A JPH02148751 A JP H02148751A
- Authority
- JP
- Japan
- Prior art keywords
- pads
- input
- output
- pad
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000005259 measurement Methods 0.000 claims abstract description 24
- 239000000523 sample Substances 0.000 abstract description 6
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の特性測定を行うためのパッドの配
置、特に入力バッドならびに出力パッド従来、半導体装
置は絶縁膜を介してバクシベーション膜開口部に測定パ
ッドを設けていた。この時の測定は、全パッドに対応し
て、測定用の針を配置したプローブカードを用いていた
。Detailed Description of the Invention [Field of Industrial Application] The present invention relates to the arrangement of pads for measuring the characteristics of semiconductor devices, particularly input pads and output pads. A measuring pad was installed in the section. For this measurement, a probe card was used that had measurement needles arranged corresponding to all the pads.
しかしながら、前述のような全パッドに対応して測定用
の針を配置したグローブカードで測定した場合のプロー
ブカードは、半導体装置の高密度化が進み、出力数が増
え、なおかつパッド間の距離が短(なった場合、測定用
の針同士が接触してしまったり、物理的に針の配置が不
可能になるといった不都合が生じるという問題がある。However, when measuring with a glove card that has measurement needles arranged corresponding to all pads as described above, the probe card has become more dense with semiconductor devices, the number of outputs has increased, and the distance between pads has increased. If the needles become too short, there are problems such as the measurement needles coming into contact with each other or making it physically impossible to arrange the needles.
また測定用のパッド数が多くなると、プローブカードの
製作が困難で針とパッド間の接続確率も著しく低下し、
接続不良により測定の効率が悪く、グローブカード自体
も高価になる。Furthermore, as the number of measurement pads increases, it becomes difficult to manufacture probe cards and the probability of connection between the needle and pads decreases significantly.
Poor connections make measurements inefficient, and the glove card itself becomes expensive.
本発明の目的は、以上の課題な改良し、高密度〔従来の
技術〕
である。The object of the present invention is to improve the above problems and achieve high density [prior art].
上記目的を達成するために、本発明は、入出力パッドを
n回の平行移動により構成した場合、接触する測定用の
針はn分の1でよいことに着目し、下記記載の構成とす
る。In order to achieve the above object, the present invention focuses on the fact that when an input/output pad is constructed by n times of parallel movement, the number of measuring needles that come into contact with it may be 1/n, and the present invention is constructed as described below. .
半導体装置表面に配置した入力端子および出力端子のパ
ッドを用いて特性測定を行なう半導体装置のパッド配置
において、分割測定回数をn回としたとき、入力端子の
パッドは同一機能を有するパッドをn列もしくはn行の
複数箇所に設け、入力端子に対応する出力端子のパッド
を入力端子の列間隔もしくは行間隔に等しい間隔で配置
する。In the pad arrangement of a semiconductor device where characteristics are measured using input and output terminal pads placed on the surface of the semiconductor device, when the number of divided measurements is n, the input terminal pads are arranged in n rows of pads with the same function. Alternatively, they are provided at a plurality of locations in n rows, and pads of output terminals corresponding to input terminals are arranged at intervals equal to the column spacing or row spacing of the input terminals.
なおここでnは2以上の正の整数である。Note that n here is a positive integer of 2 or more.
以下、図面に基づいて本発明の詳細な説明する。第1図
は本発明の一実施例で例えば2分割測定の場合を示す。Hereinafter, the present invention will be described in detail based on the drawings. FIG. 1 shows one embodiment of the present invention, for example, in the case of two-part measurement.
半導体基板表面のスクライブライン12で区画された領
域が、1つの半導体チップを示し、この半導体チップの
四角で示す部分はパッドを示し、斜線のあるパッド12
6〜128は入力のパッドを示す。101〜122は出
力のパッドを示す。入力のパッド126と124゜12
5と126,127と128は同一の信号が入力される
。入力端子群のパッド間の間隔量はdで、出力端子はと
のdに対応して分散配置される。A region demarcated by scribe lines 12 on the surface of the semiconductor substrate represents one semiconductor chip, and square portions of this semiconductor chip represent pads.
6 to 128 indicate input pads. 101 to 122 indicate output pads. Input pads 126 and 124°12
The same signals are input to 5 and 126, 127 and 128. The spacing between pads of the input terminal group is d, and the output terminals are distributed in correspondence to d.
第1回の測定において、測定用の針14は実線16で示
すごとく奇数番号のパッドに接触し、測定を行う。第2
回の測定においてはプローブカードはピッチdだげ移動
し、破線18で示す測定用の針のごと(偶数番号のパッ
ドに接触する。In the first measurement, the measuring needle 14 contacts odd-numbered pads as shown by the solid line 16 and takes measurements. Second
In the second measurement, the probe card moves by a pitch d and contacts the even numbered pads of the measuring needles indicated by broken lines 18.
第2図は3分割測定の場合のパッド配置を示す。FIG. 2 shows the pad arrangement in the case of three-part measurement.
201.202.206の組と204,205.206
の組と207.208,209の組は同一の機能を有す
る入力端子群のパッドを示し、210〜218は入力端
子群のピッチに対応して分散配置された出力端子のパッ
ドを示す。第1回の測定ではパッド201.204.2
07.210.213.216が使用され、第2回にお
いては、パッド202.205.208.211.21
4.217が使用され、第3回の測定においてはパッド
°206.206.209.212.215.218が
使用される。以上のように、本発明によれば、使用する
グローブカードの測定用の針の数は、n回の分割測定に
おいて、ですみ、測定用の針の数を疎にし、プローブカ
ードの作成を容易にすることが可能となる。The pair 201.202.206 and 204,205.206
The set 207, 208, and 209 indicate input terminal pads having the same function, and 210 to 218 indicate output terminal pads distributed in correspondence with the pitch of the input terminal group. In the first measurement, pad 201.204.2
07.210.213.216 is used, and in the second time pad 202.205.208.211.21
4.217 is used and in the third measurement pad °206.206.209.212.215.218 is used. As described above, according to the present invention, the number of measuring needles of the glove card used is only required in n divisional measurements, and the number of measuring needles is sparse, making it easy to create a probe card. It becomes possible to
以上の説明から明らかなように、本発明によれば入力バ
ッドならびに出力パッドが高密度に集積された半導体装
置の測定において、グローブカードを容易に作成可能と
し、複数回の分割測定によって同一のグローブカードで
全出力のチエツクを可能とすることができ、さらに、接
続確率を向上させ、測定の効率を上げ、グローブカード
な安価にすることができる。また、ここで用いた平行移
動の方向は、横方向でもよい。測定の分割数も実施例で
示した2回、3回に限定されず複数回の分割測定が可能
である。As is clear from the above description, according to the present invention, it is possible to easily create a glove card in the measurement of semiconductor devices in which input pads and output pads are densely integrated, and the same glove card can be easily created by performing multiple divided measurements. It is possible to check the full output with the card, and furthermore, the connection probability can be improved, the measurement efficiency can be increased, and the price of the glove card can be reduced. Further, the direction of parallel movement used here may be the lateral direction. The number of divided measurements is not limited to two or three times as shown in the embodiments, but multiple divided measurements are possible.
第1図および第2図はいずれも本発明のパッド配置を示
し、第1図は一実施例、第2図は他の実施例のそれぞれ
説明図である。
12・・・・・・スクライブライン、
14・・・・・・測定用の針、
101〜128.201〜218・・・・・・パッド。
第2図Both FIG. 1 and FIG. 2 show the pad arrangement of the present invention, with FIG. 1 being an explanatory diagram of one embodiment, and FIG. 2 being an explanatory diagram of another embodiment. 12...Scribe line, 14...Measuring needle, 101-128.201-218...Pad. Figure 2
Claims (1)
ッドを用いて特性測定を行なう半導体装置のパッド配置
において、分割測定回数をn回としたとき、該入力端子
の該パッドは同一機能を有する前記パッドをn列もしく
はn行の複数箇所に設け、前記入力端子に対応する該出
力端子の前記パッドを前記入力端子の列間隔もしくは行
間隔に等しい間隔で配置することを特徴とする半導体装
置のパッド配置構造。In a pad arrangement of a semiconductor device in which characteristics are measured using pads of an input terminal and an output terminal arranged on the surface of a semiconductor device, when the number of divided measurements is n times, the pad of the input terminal is the same as the pad having the same function. are provided in a plurality of locations in n columns or n rows, and the pads of the output terminals corresponding to the input terminals are arranged at intervals equal to the column spacing or row spacing of the input terminals. structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30182688A JPH02148751A (en) | 1988-11-29 | 1988-11-29 | Pad layout for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30182688A JPH02148751A (en) | 1988-11-29 | 1988-11-29 | Pad layout for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02148751A true JPH02148751A (en) | 1990-06-07 |
Family
ID=17901628
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30182688A Pending JPH02148751A (en) | 1988-11-29 | 1988-11-29 | Pad layout for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02148751A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0582605A (en) * | 1991-09-24 | 1993-04-02 | Mitsubishi Electric Corp | Semiconductor integrated circuit element and wafer test inspection |
| JPH07201935A (en) * | 1993-12-28 | 1995-08-04 | Nippon Maikuronikusu:Kk | Probe card and inspection method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57113266A (en) * | 1980-12-29 | 1982-07-14 | Seiko Epson Corp | Wiring method for active matrix substrate |
| JPS63181339A (en) * | 1987-01-22 | 1988-07-26 | Oki Electric Ind Co Ltd | Inspection of integrated circuit element |
-
1988
- 1988-11-29 JP JP30182688A patent/JPH02148751A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57113266A (en) * | 1980-12-29 | 1982-07-14 | Seiko Epson Corp | Wiring method for active matrix substrate |
| JPS63181339A (en) * | 1987-01-22 | 1988-07-26 | Oki Electric Ind Co Ltd | Inspection of integrated circuit element |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0582605A (en) * | 1991-09-24 | 1993-04-02 | Mitsubishi Electric Corp | Semiconductor integrated circuit element and wafer test inspection |
| JPH07201935A (en) * | 1993-12-28 | 1995-08-04 | Nippon Maikuronikusu:Kk | Probe card and inspection method |
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