JPH02148984A - Image information reproducing device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a reproducing device in a system for recording and reproducing digital image information, and particularly relates to a reproducing device suitable for easily detecting a signal-free portion of a recording medium. The present invention relates to a digital image information reproducing device.

[Conventional technology]

In conventional digital image information recording and reproducing apparatuses, emphasis has been placed on protection in the event that a reproduction signal from a recording medium is lost, as described in Japanese Patent Laid-Open No. 156076/1983. The reproduced digital image data is once stored in the memory and then read out and outputted. If a loss of the reproduced signal is detected, writing to the memory is stopped, so that data related to the image, for example one frame before, can be read again. This prevents disturbances in the reproduced image information.

[Problem to be solved by the invention]

However, the above-mentioned conventional technology does not give consideration to the point of making it easy to detect signal-free areas, and when a signal-recording medium reaches a signal-recording area during playback, the data is stored in the memory in the same way as when a signal is missing. Since writing is stopped, the image information stored in the memory immediately before the non-recorded portion is repeatedly reproduced as a still image, causing a problem in that the beginning of the non-recorded portion cannot be easily and accurately detected.

An object of the present invention is to eliminate the drawbacks of the prior art as described above, and to provide digital image information that can easily detect a non-recorded part even when it reaches a non-recorded part during playback, and that can be accurately determined by visual inspection. The purpose is to provide a playback device.

[Means for Solving the Problem] The above object is achieved by outputting noise to the reproduced image signal in the signal-free portion. As a result, it is possible to detect unrecorded portions without feeling strange because noise appears on the entire playback screen in the same way as with an analog recording type VTR.

Outputting noise on the screen can be achieved by replacing the output image data portion with an M-sequence pseudo-random signal in the digital domain. If the period of the M sequence is too short, periodic bangs will appear on the screen, and a sufficient effect will not be obtained. On the other hand, even if one bit (or one word) of the M-sequence pattern is replaced with multiple pixels, a sufficient effect can be obtained. against, 10
We have discovered that a good noise screen can be obtained by replacing one bit of M-sequence bangs with a period of 23 or more with 4 samples of image data.

In addition, in a playback device that once stores playback image data in a memory and then reads and outputs the image data, noise can also be generated on the screen by replacing the readout address with an M-sequence pattern word. . Furthermore, even if signal loss is detected, if it can be determined that the signal is not recorded, the noise data reproduced from the recording medium may be output as is without stopping writing to the memory. This can be achieved by removing the error flag used for

- Determination of a non-force recording portion is possible by detecting that the reproduction signal level from the medium has been below a certain value for a certain period of time or more. Furthermore, if the data is recorded using a modulation method having a predetermined rule, it may be detected that the appearance frequency of a signal that deviates from the rule exceeds a certain value. Furthermore, the unrecorded portion can also be determined by detecting that the detection rate of the synchronization signal or identification signal has become less than a predetermined value, or that the code error rate of the reproduced signal has become more than a predetermined value.

[Effect]

When it is determined that there is no signal recorded due to a decrease in the level of the reproduced signal from the medium, at least the valid pixel portion of the reproduced digital image signal is replaced with random data by the function of a data selector, memory address selector, etc. It will be done. As a result, the output image signal restored to an analog signal becomes a noise screen, and the beginning of a non-recorded portion can be easily detected.

On the other hand, 1. For example, in a digital recording VTR that has multiple reproducing rotary heads, a signal-free portion is detected only when the respective reproduced signals from multiple heads have the same level drop or increase in code errors. It's good to judge. This makes it possible to prevent malfunctions that would generate large noises when only some of the heads come out abnormally due to head clogging or the like.

〔Example〕 The details of the present invention will be explained below using examples.

FIG. 1 is an embodiment diagram showing the basic block configuration of an image information reproducing apparatus according to the present invention. In FIG. 1, 1 is a signal input terminal, 2 is a signal processing circuit, 3 is a noise generation circuit,
4 is a signal detection circuit, 5 is a control circuit, 6 is a switching circuit, and 7 is a signal pressure circuit.

A signal reproduced from a signal recording medium by a magnetic head or the like is input from a signal input terminal 1 to a signal processing circuit 2 and a signal detection circuit 4. The signal processing circuit 2 performs data demodulation, error correction, and
After performing corrections and D/A conversion, a signal that becomes an image signal is output to the switching circuit 6. The noise generating circuit 3 generates a digital noise signal and outputs it to the switching circuit 6.

On the other hand, the signal detection circuit 4 monitors the input signal from the signal input terminal l, and if there is no input signal even though it is in the reproduction state, a determination signal indicating that there is no signal recording portion is sent to the control circuit. Output to 5. When the control circuit 5 receives a determination signal from the signal detection circuit 4 indicating that no signal is recorded on the signal recording medium currently being reproduced, that is, a signal-free portion, the control circuit 5 outputs the digital image from the signal processing circuit 2. A switching control signal is output to the switching circuit 6 so as to replace the effective pixel portion of the signal with the digital noise signal from the noise generating circuit 3. The switching circuit 6 outputs the digital image signal from the signal processing circuit 2 to the signal output terminal 7 when a signal is recorded on the recording medium being played back, and outputs the digital image signal from the signal output terminal 7 to the effective pixel when no signal is recorded. part is switched to a digital noise signal from the noise generating circuit 3 and outputted to the signal output terminal 7.

As described above, in the present invention, if no signal is recorded on the signal recording medium, noise will appear on the display screen of the image signal obtained by D/A converting the output signal of the signal output terminal 7, and unrecorded portions will be easily detected. can. In the embodiment shown in FIG. 1, it has been explained that switching between the image signal and the noise is performed using the signal immediately before the D/A, but of course the same effect can be obtained by switching between the image signal and the noise on other signals. For example, in a digital VTR, signal data is rearranged called shuffling in order to suppress deterioration of playback image quality even when there are many code errors. good. As a configuration example of the noise generation circuit 3 that digitally generates noise in this manner, an M-sequence generator that generates a pseudo-random signal can be used. Further, even if switching is performed in the area of analog signals after D/A conversion, the same effect of the present invention can be obtained. Of course, in that case, the noise generation circuit 3 is changed to generate an analog noise signal. An example of such an analog noise signal generator is one using a diode.

Next, details of the case where the noise generating circuit 3 of the present invention is constituted by an M-sequence generator will be explained using the embodiment shown in FIG.

FIG. 2 is a block diagram showing an embodiment in which the noise generating circuit 3 of the image information reproducing apparatus according to the present invention is constituted by an M-sequence generator. In FIG. 2, 8 and 9 are serial input/parallel output 8-bit shift registers, and 10 is an Ex-OR gate.

11 is a data sampling circuit.

In the embodiment shown in FIG. 2, a signal input terminal 1, a signal processing circuit 2
, the signal detection circuit 4, the control circuit 5, the switching circuit 6, and the signal output terminal 7 are similar to those in the embodiment shown in FIG. I will only explain. Although the same applies to each of the following embodiments, an example will be described in which the input digitized image information is an 8-bit quantized composite video signal. Shift registers 8 and 9 are 7-bit and 8-bit shift registers, respectively, and at least one or all of these bits can be initialized to "1". Further, the subsequent shift register 9 has parallel outputs for each bit.

For both of these shift registers 8 and 9, for example, 5N74198 manufactured by TI Corporation can be used. In addition, the second
In the figure, these are clock terminals of shift registers 8 and 9.

Descriptions of load terminals, load data terminals, etc. for initialization are omitted.

The 7th bit output QO of the shift register 8 is connected to the serial input terminal SIN of the shift register 9 and the Ex-OR gate 1.
It is input to 0. The 8th bit output Q of the shift register 9 is inputted to the other input terminal of the Ex-OR gate 10. The output of the Ex-OR gate 10 is input to the serial input terminal SIN of the shift register 8. In this way, the shift registers 8 and 9 and the Ex-OR gate 10
An M sequence generator with 5 bits and sequence length of 32767 is constructed. It goes without saying that the same effects of the present invention can be obtained even if a 1M sequence generator with other register lengths and feedback configurations is used. However, if the sequence length is too short, a problem will occur where periodic bangs will be visible on the screen, which is not very desirable.

The shift registers 8 and 9 are initialized by loading (presetting) each bit with 11171 before the playback device starts operating. A clock having a frequency eight times that of the transfer lock of the 8-bit parallel data output of the signal processing circuit 2 is input to the shift clock input terminal of the shift register 8.9, and a pseudo-random signal is generated. The output Q A ''Q u of each bit of the shift register 9 is inputted to a data extraction port path 11 respectively.Data extraction circuit 11
is the output of each bit of shift register 9 once every 8 times when shift registers 8 and 9 shift data.
u is extracted and output to the switching circuit 6. The data extracting circuit 11 also functions to suppress the level of the output signal within the level range of the video signal when the extracted 8-bit output of the shift register 9 has a value outside the video signal level range of the composite video signal. Specifically, it is compared with the pedestal level value using, for example, an 8-bit magnitude comparator, and if the extracted output of the shift register 9 is less than the pedestal level, the output of the sampling circuit 11 is replaced with the pedestal level value. Thereby, unnecessary malfunctions of various circuits connected after the signal output terminal 7 can be avoided. Hereinafter, when the non-signal recording portion of the signal recording medium is reproduced by the operation of each part similar to that of the embodiment shown in FIG.
Immediately generates a noise screen. The function of suppressing the level of the sampling circuit 11 within the video signal level range is not necessary when the image information is not a composite video signal and the image signal level covers the entire range of 8-bit digital data. Needless to say, even if this is the case, it is not essential. In addition.

It is also possible to stop the shift clocks of the shift registers 8 and 9 except for the period corresponding to the period in which the effective pixel portion is output from the signal processing circuit 2, thereby suppressing the generation of unnecessary noise signals.

Next, a case where the noise generating circuit 3 of the present invention has a different configuration using an M-sequence generator will be described using the embodiment shown in FIG. FIG. 3 is a block diagram of an embodiment in which the noise generating circuit 3 of the image information reproducing apparatus according to the present invention is a circuit using an M-sequence generator having a different configuration from that of the embodiment of FIG. In FIG. 3, 12 is a selector that outputs one of two types of input data.

In the embodiment shown in FIG. 3, as well as in the embodiment shown in FIG.
Shift registers 8, 9 .corresponding to the noise generator 3 in the illustrated embodiment. Since the functions and operations of each part other than the Ex-OR gate 10 and selector 12 are similar to those in the embodiment shown in FIG. 1, only the part corresponding to the noise generator 3 will be described.

The connection between the shift register 8.9 and the Ex-OR gate 10 is 15 bits and the sequence length is 327, the same as in the embodiment shown in FIG.
67 M-sequence generators are constructed. Of course, other configurations of the M-sequence generator are possible.

Similar to the embodiment shown in FIG. 2, the shift registers 8 and 9 are initialized at the start of operation of the playback device. shift register 8
, 9 receives a clock having the same frequency as the transfer lock of the 8-bit parallel data output of the signal processing circuit 2, unlike the embodiment shown in FIG. In this way, a pseudorandom signal is generated at the output of the Ex-OR gate 10, and the select signal input terminal S of the selector 12
is input. The selectors 12 each have 8 bits A,
10'''IJ I IT of select signal for 82 sets of inputs
In this embodiment, the pseudo random signal input to the select signal input terminal S is outputted according to the LLO
When it is IT, it is the black level signal input to the A terminal (here, 3C in hexadecimal notation), and when it is '1'', it is the white level signal input to the B terminal (here, in hexadecimal notation, "F").
F'') is output to the switching circuit 6.Then, the output of the selector 12 becomes a noise signal in which the white level and black level appear randomly.Of course, the L of the pseudorandom signal
It goes without saying that the correspondence between I OIItz 1 u and the black level and white level may be reversed, and the signal level itself is not limited to the black level and white level, but may be any other level. Further, the A and B inputs of the selector 12 may be respectively set as separate 8-pips 1- pseudorandom signals.

Hereinafter, by operating the same parts as in the embodiments of FIGS. 1 and 2, when a signal-free portion of the signal recording medium is reproduced, a noise screen is immediately generated. In addition, as in the embodiment shown in FIG. 2, the shift clocks of the shift registers 8 and 9 are stopped except for the period corresponding to the period in which the effective pixel portion is output from the signal processing circuit 2, thereby generating unnecessary noise signals. It is also possible to suppress

Furthermore, in both the embodiments of FIGS. 2 and 3, the shift register 8,
A good effect can be obtained even if the shift clock of 9 is divided by an integer. For example, in the embodiment shown in FIG. 3, if the image information signal is an NTSC composite color signal and is sampled at a frequency (4 fsc) four times that of the color subcarrier, the 8-bit parallel data output of the signal processing circuit 2 is The transfer lock is 4fsc. Here, if the shift clock of shift register 8.9 is set to 1/4 fsc, the level of the noise screen signal output when no signal is recorded changes according to the M series every 4 pixels, so the frequency of the fundamental wave is fsc/2, and an easy-to-see black and white noise screen with no color flickering is obtained. In the embodiment shown in FIG. 2, it is necessary to extend not only the shift clocks of the shift registers 8 and 9 but also the sampling period of the data sampling circuit 11 by an integral multiple.

The present invention can be implemented with a configuration other than the above-described configuration in which the output signal is switched to a signal from a noise generator.6 Next, another configuration of the present invention will be explained with reference to the embodiment shown in FIG. FIG. 4 is a block diagram showing an embodiment of the image information reproducing apparatus according to the present invention implemented by memory address control. In FIG. 4, 13 is a memory, 14 is a switching circuit for switching between a write address and a read address, 15 is a write address generation circuit, 16 is a read address generation circuit, and 17
are the M-sequence generator (shift register 8, 9, Ex-OR gate 10, data extraction circuit 11) in the embodiment shown in FIG.
18 is a switching circuit.

A reproduced signal from a signal recording medium inputted from a signal input terminal 1 is inputted to a signal processing circuit 2 and a signal detection circuit 4. The signal processing circuit 2 detects and corrects code errors that occur in the reproduced signal, writes the corrected data into the memory 13, reads the data from the memory 13, and displays it as an image signal after D/A conversion from the signal output terminal 7. It performs various signal processing and outputs it. Here, for data in which code errors cannot be corrected and errors remain, the signal processing circuit 2 adds an error flag and stops writing the data to the memory 13. A write address from a write address generation circuit 15 and a read address from a read address generation circuit 16 via a switching circuit 18 are applied to the memory 13 by a switching circuit 14 according to each mode of writing and reading. Write and read address generation circuit 15
The memory address from ゜16 is set to be the same address for each fixed amount of image information, for example, the address of the data of the nth pixel from the beginning on one screen, and the address of the next pixel that has a high correlation with this data. The address of the data of the nth pixel from the top on the screen is set to be the same address, and even if a code error in certain data cannot be corrected and is not written to the memory 13, there is a strong correlation with this. Since the data remains at the corresponding address location in the memory 13 and can be read out, deterioration in reproduced image quality can be prevented.

On the other hand, the signal detection circuit 4 monitors the input signal from the signal input terminal 1 as in the embodiment shown in FIG. A determination signal indicating that this is the case is output to the switching circuit 18. Upon receiving this determination signal, the switching circuit 18 writes the pseudo-random data from the M-sequence generator 17 in the areas where the signal is not recorded, and writes the regular read address from the read address generation circuit 16 in the areas where the signal is recorded. .

Selective output is made to the switching circuit 14 that switches the read address. As a result, the read address of the memory 13 becomes random in the signal-free portion, and as a result, the image signal outputted from the signal processing circuit 2 via the signal output terminal 7 becomes a random noise image. The same effects as in the embodiment can be obtained.

Similarly to the embodiment shown in FIG.
This will be explained using figures. FIG. 5 is a block diagram showing another embodiment of the image information reproducing apparatus according to the present invention. Fifth
In the figure, 19 is an arithmetic circuit.

In the embodiment shown in FIG. 5, the switching circuit 18 shown in FIG.
9, and only that part will be explained here. The arithmetic circuit 19 uses a gate controlled by the determination signal from the signal detection circuit 4 and adds the random data from the M sequence generator 17 via this gate to the value of the read address from the read address generation circuit 16 modulo 2. It consists of a computing unit that performs When the judgment signal from the signal detection circuit 4 indicates a signal-free portion, the gate is opened, and the value obtained by adding the M-sequence pseudo-random data modulo 2 to the value of the read address, that is, a random value, is stored in the new memory. The memory 13 is read as a read address via the switching circuit 14.
is output to. - If the power signal is recorded, the gate is closed by the determination signal, and the value from the read address generation circuit 16 is output as is.

As described above, in the embodiment shown in FIG. 5, as well as in the embodiment shown in FIG. 4, a noise screen is generated immediately when a signal-free portion is reached during reproduction. Although the arithmetic unit in the arithmetic circuit 19 is modulo-2 addition in the explanation of this embodiment, it can be used for ordinary addition, subtraction,
Other arithmetic units such as multiplication and division may also be used.

Furthermore, in both the embodiments shown in FIGS. 4 and 5, the M sequence generator 17
The shift clock may have the same frequency as the memory read cycle, but it is also effective to set it to an integer fraction thereof, as described in the embodiments of FIGS. 2 and 3. Furthermore, in the embodiment shown in FIG. 5, the operating clock of the read address generation circuit 16 may be set to a fraction of an integer only in the signal non-recorded portion.

FIG. 6 is a block diagram showing an embodiment in which the present invention is realized by still another means. In FIG. 6, 2 is a signal processing circuit including an error correction circuit, and 20 is a write/read address generation circuit for the memory 13.

21 is an OR gate, and 22 is an AND gate.

Similarly to the embodiments shown in FIGS. 4 and 5, the reproduced signal input from the signal input terminal 1 has code errors detected and corrected by the signal processing circuit 2, and is stored in the memory controlled by the address circuit 20. 13. A write pulse WE is sent from the signal processing circuit 2 to the memory 13 via the OR gate 21, and data is written into the memory 13 when WE becomes IIOII. The signal detection circuit normally outputs '1' as a judgment signal to the AND gate 22 during signal reproduction, and when a signal non-recorded portion is detected, this judgment signal becomes '11'.
It becomes 0″″. Furthermore, if there is a code error that cannot be corrected in the data written to the memory 13 by the signal processing circuit 2, the signal processing circuit 2 sets the EF multiplied signal "1" to the AN
Output to D gate 22.

If there is no error, L'0'' is output to the AND gate 22. Therefore, if there is a code error that cannot be corrected in the part where the signal is recorded on the signal recording medium, the EF multiplied signal is output from the AND gate 22. Appears as “1”,
The output of the OR gate 21 remains "1" even if the WE pulse from the signal processing circuit 2 becomes "O", and no data is written to the memory 13. Thus, in the description of the embodiment of FIG. As described above, deterioration in image quality due to incorrect image data can be prevented.

On the other hand, when the unrecorded signal portion is reproduced, the input signal to the signal processing circuit 2 becomes a digital noise signal, and the data written to the memory 13 becomes a random signal. Also,
Naturally, it cannot be corrected, so the EF high output becomes ``1''. However, at this time, the judgment signal of the signal detection circuit 4 is II O11
Since the AND gate 22 is closed and its output becomes "0", the WE pulse is directly transmitted to the memory 13, and a random signal is written to the memory 13.
Therefore, in the signal-free portion, the signal read out from the memory 13 by the signal processing circuit 2 and output from the signal output terminal 7 becomes a random signal, generating a noise screen as in each of the previous embodiments. In addition.

In this example, in order to simplify the explanation, an AND gate and an OR gate are used.
Although a gate was used, it goes without saying that a similar circuit can be realized with other gate configurations.

Next, an example of the configuration of a circuit for detecting a signal-free portion, which is described as the signal detection circuit 2 in each of the embodiments shown in FIGS. 1 to 6, will be explained in detail with reference to FIGS. 7 to 11. 7 to 11 are block diagrams showing embodiments of the signal detection circuit 2 constituting the image information reproducing apparatus according to the present invention. First, the embodiment shown in FIG. 7 will be described. In FIG. 7, 23 is a reproduced signal input terminal, 24 is a signal level detection circuit, 25 is a comparator, 26 is a reference voltage source, 27 is a pulse width detection circuit,
28 is a digital comparator, and 29 is a judgment signal output terminal.

A signal reproduced from a signal recording medium by a magnetic head or an optical pickup is input to a signal level detection circuit 24 via a reproduced signal input terminal 23.

The level detection circuit 24 is a so-called envelope detection circuit, and outputs a voltage according to the envelope of the signal from the reproduced signal input terminal 23. The output of the level detection circuit 24 is input to a comparator 25 and compared with a predetermined value from a reference voltage source 26. Comparator 25 is level detection circuit 24
LOW if the output voltage is higher than the voltage of the reference voltage source 26
If the level is low, a HIGH level is output. That is, when a signal is recorded on a signal recording medium and a reproduced signal envelope is output, the output voltage of the level detection circuit 24 is set to be higher than the voltage of the reference voltage source 26, and in this case, the comparator 25 output is LOW
level. - When a signal is not recorded on the force signal recording medium, the reproduced signal envelope disappears, so the output voltage of the level detection circuit 24 becomes lower than the voltage of the reference voltage source 26, and the output of the comparator 25 rises to the HIGH level. The output of the comparator 25 is input to a pulse width detection circuit 27, which measures the length of the HIGH level section, that is, the length of the section in which the reproduced signal envelope falls below a predetermined value. In other words, the pulse width detection circuit 27
is composed of a counter that is reset when the output of the comparator 25 is at LOW level, and counts clocks of a predetermined frequency when it goes to HIGH level. The count output of the pulse width detection circuit 27 is input to the A terminal of the digital comparator 28 and compared with a predetermined reference value also input to the B terminal.

In this way, when the section becomes a signal non-recording section and the reproduced signal envelope decreases, it becomes longer than a predetermined value.

The A<B output of the digital comparator 28 is inverted from 111 II to 0'', and this signal is output from the judgment signal output terminal 29 as a judgment signal. In this manner, the pulse width detection circuit 27 and the digital comparator 29 function to distinguish between an instantaneous reproduction signal envelope and a drop due to dropout or the like. Further, the pulse width detection circuit 27 is connected to the comparator 2
It is not necessary to keep counting the HIGH section of the 5 output, but when the reference value input to the B terminal of the digital comparator 28 is exceeded, the count is stopped, and then the output of the comparator 25 becomes LOW and is reset. It can be configured to count when it becomes HIGH again.

Next, the embodiment shown in FIG. 8 will be explained. In FIG. 8, 30 is a reproduction signal input terminal, 31 is a demodulation circuit, 32 is a reproduction error detection circuit, 33 is a counter, 34 is a control circuit, 35 is a latch, and 36 is a digital signal output terminal.

A signal reproduced from a signal recording medium by a magnetic head or an optical pickup and digitized by a data strobe circuit is input to a demodulation circuit 31 via a reproduced signal input terminal 3o. The demodulation circuit 31 uses a predetermined recording modulation method performed during recording, such as MFM, M", EFM, 3PM,
8-10 Convert input digital signal to N in response to conversion, etc.
It is demodulated into an RZ format digital signal and output to a subsequent digital signal processing circuit via the digital signal output terminal 36.

The reproduction error detection circuit 32 monitors the demodulation circuit 31, checks whether the input digital signal conforms to a predetermined modulation rule, and outputs a pulse to the counter 33 if a signal deviating from the rule is detected. Taking MFM and M2 modulation as an example, the polarity reversal interval of the modulation signal is the bit period T.
Then T.

Since the polarity is limited to 1.5T and 2T (furthermore, 2.5T and 3T for M2), if the polarity is reversed at intervals other than these, it is detected using a counter or a slam comparison circuit, and a pulse is output. The counter 33 is reset at a predetermined period by the control circuit 34, and the above-mentioned reproduction error detection circuit 32
Count the pulses from. The control circuit 34 is a counter 33
A latch pulse is sent to the latch 35 immediately before resetting the counter 33 that is input at that time.
The error count value of is latched.

If the signal is recorded on a signal recording medium.

Although the reproduced signal input from the reproduced signal input terminal 30 to the demodulation circuit 31 contains some code errors due to recording and reproduction,
is a signal that almost always conforms to a predetermined modulation rule. Therefore, while being reset by the control circuit 34, the counter 3
The count value counted by 3 and transferred to latch 35 is not very large. On the other hand, in the signal-free portion, the reproduced signal is a random signal and contains many signals that do not conform to the predetermined modulation rules. Therefore, the count value transferred to latch 35 at this time becomes large. The output of this latch 35 is input to the A terminal of the digital comparator 28, while the B terminal of the digital comparator 28 is input with a value approximately halfway between the above two count values as a reference value, so that A< The determination signal outputted from the B output terminal via the determination signal output terminal 29 is similar to the embodiment shown in FIG. 7, and if the signal is recorded, II I 11.
In the part where no signal is recorded, it becomes 110 ++, and is used for generating a noise screen by each signal processing in the subsequent stage.

Next, the embodiment shown in FIG. 9 will be described. In FIG. 9, 37 is a synchronization signal detection circuit.

A synchronization detection circuit 37 detects a synchronization signal inserted in the digital reproduction signal input from the reproduction signal input terminal 30 to synchronize data, and the detected reproduction signal is sent to the digital signal output terminal 36. The signal is then sent to the subsequent signal processing circuit. The synchronization detection circuit 37 outputs a pulse to the counter 33 every time it detects a synchronization signal. The counter 33 is controlled by a control circuit 34 as in the embodiment shown in FIG. 8, and the count value is transferred to the latch 35 at regular intervals. When signals are recorded on a recording medium, almost all synchronization signals except when a code error occurs are detected, so the counter 33 is transferred to the latch 35.
The count value will be a large value, but if no signal is recorded, almost no signal similar to the synchronization signal will be detected, so the count value will be a small value. latch 3
The output of 5 is input to the B terminal of the digital comparator 28,
On the other hand, an appropriate set value between the above two values is inputted to the A terminal of the digital comparator 28 as a reference value.

Therefore, the judgment signal output from the A<B terminal of this digital comparator 28 to the judgment signal output terminal 29 is
As in the embodiment shown in the figure, the value is 1" in the signal recording portion, and the value is "OIT" in the non-recording portion.

Further, the embodiment shown in FIG. 10 will be explained. In FIG. 10, 38 is an error correction circuit.

The digital playback signal input from the playback signal input terminal 30 enters the error correction circuit 38, detects and corrects code errors that occur during the re-recording process, and then sends it from the digital signal output terminal 36 to the subsequent signal processing circuit. It will be done. When the error correction circuit 38 detects a code error in the reproduced signal, it outputs an error detection pulse to the counter 33. Counter 33, control circuit 34, latch 35. The digital comparator 28 outputs the judgment signal output terminal 2 from the A>B terminal of the digital comparator 28.
except that the judgment signal is output at 9.

This is similar to the embodiment shown in FIG. Therefore, when a predetermined signal is recorded on the signal recording medium, the number of code errors detected by the error correction circuit 38 and counted by the counter 33 is not so large.On the other hand, when no signal is recorded, the input reproduction signal is Since all of them are errors, the count value of the counter 33 becomes a large value.

Therefore, if the reference value of the A terminal of the digital comparator 28 is set to a value between these values, the judgment signal will be
1 u, "O11" in the unrecorded portion 6 Note that the same effect can be obtained even if the error correction circuit 38 outputs a pulse to the counter 33 when correction becomes impossible.

Next, the embodiment shown in FIG. 11 will be described. In FIG. 11, 39 is an ID detection circuit, and 40 is a rule checking circuit. In this embodiment, identification information (ID information) is used as additional information for identifying the content of data for each predetermined data in the signal.
has been inserted.

It is assumed that a part of the information includes data block number information that is incremented for each data block.

The playback signal input from the playback signal input terminal 30 is
ID information is extracted by the detection circuit 39, and subsequent signals are output from the digital signal output terminal 36. The ID detection circuit 39 sends the extracted ID information to the rule checking circuit 40. Here, if the signal is recorded on the signal recording medium, the extracted ID information is almost correct, and in this embodiment, it includes a part that is incremented for each data block. On the other hand, since the ID information is not extracted correctly in the unrecorded portion, the above-mentioned increment portion does not exist. The rule checking circuit 40 of this embodiment checks whether an increment portion of this ID information exists, that is, whether or not it is incrementing correctly. If the increment portion exists, it outputs a pulse to the counter 33. Therefore, the counter 33, the control circuit 34, the latch 35, the digital comparison circuit 28, and the judgment signal output terminal 29, which have the same configuration as the embodiment shown in FIG. The judgment signal is 1
'', and in the unrecorded part, the count value becomes smaller than the reference value, and the judgment signal becomes IIO11.The rule checking circuit 4o uses, for example, a method of checking whether the fixed data part of the ID information is correct based on a click match. But okay,
Furthermore, if there is a part in the ID information that repeats periodic changes, a method may be adopted in which it is checked.

Finally, in a system that reproduces signals from a signal recording medium using a plurality of magnetic heads, etc., a signal detection circuit as shown in FIGS. It can be configured to generate a noise screen when both judgment signals from the circuit indicate a signal-free portion. As in each of the embodiments described so far.

The judgment signal is 1" in the signal recording part and 110 in the non-recording part.
In the configuration M, noise screen generation may be controlled by calculating the logical sum of the determination signals of each signal detection circuit (for example, by using the control circuit 4 in the embodiment shown in FIG. 1). This can result in, for example, a long-term loss of the reproduced signal due to clogging of the magnetic head (in many cases, the output of only one head is reduced).
It is possible to distinguish between signal-free areas (where the entire reproduced signal is missing), correctly generates noise images only in signal-free areas, and obtains images with less deterioration by correcting errors such as magnetic head clogging. be able to.

In each of the above embodiments, the present invention is realized using hardware.
It goes without saying that the regularity of D can also be determined by software. Even in that case, there is no change in the effects and effectiveness of the present invention.

Furthermore, when the image information is a decoded video signal, if the shift registers 8 and 9 that generate the M sequence are initialized, for example, once every four fields in the embodiments shown in FIGS. It's like moving on the screen like a bang, M
Problems caused by the periodicity of the series itself can be avoided,
A good noise screen can be obtained. Of course, the same effect can be expected even if initialization is performed once for a different number of fields.

In addition, in a helical scan type digital VTR, the presence or absence of recording signals in linear track sections such as control tracks and time code tracks can be used to inspect unrecorded sections.

〔Effect of the invention〕

According to the present invention, even when a non-recorded portion is reached during playback, it is possible to easily detect that the non-recorded portion has been reached.
Also in a digital image information reproducing device, there is an effect that the start of a signal-free portion can be accurately determined by visual confirmation.

[Brief explanation of the drawing]

FIGS. 1 to 6 are block diagrams showing embodiments of the overall configuration of the present invention, and FIGS. 7 to 11 are block diagrams showing embodiments of the signal detection circuit portion thereof. 2... Signal processing circuit, 3... Noise generation circuit, 4.
...Signal detection circuit, 5...Control circuit, 6...Switching circuit, 8.9...Shift register, 10...ExOR
Gate, 13...Memory, 17...M sequence generation circuit, 24...Level detection circuit, 25...Comparator, 27...Pulse width detection circuit, 28...Digital comparator, 31. ... Demodulation circuit, 32 ... Reproduction error detection circuit, 33 ... Counter, 37 ... Synchronization detection circuit, 38 ... Error correction circuit, 39 ... ID detection circuit,
40... Rule inspection circuit.

Claims (1)

[Claims] 1. Digitizing image information and recording it on a recording medium;
In a reproducing device of an image information recording and reproducing system that restores a digital signal reproduced from a recording medium to image information and outputs the image information, if no signal is recorded on the recording medium, at least the effective pixel portion of the reproduced image information is An image information reproducing device characterized in that part or all of the signal is replaced with a random signal and output. 2. Digitize the image information and record it on a recording medium,
In a reproducing device of an image information recording and reproducing system that restores a digital signal reproduced from a recording medium to image information and outputs the image information, if no signal is recorded on the recording medium, at least the effective pixel portion of the reproduced image information is An image information reproducing apparatus characterized in that digital data corresponding to part or all of the data is replaced with M-sequence pseudo-random data, and then restored to image information and outputted. 3. In a reproducing device of an image information recording and reproducing system that digitizes image information with a quantization bit number n and records it on a recording medium, and restores the digital signal reproduced from the recording medium to image information and outputs the image information, If no signal is recorded on the recording medium, digital data corresponding to at least part or all of the effective pixel portion of the reproduced image information is replaced with data obtained by dividing M-sequence pseudorandom data into n bits, and then the image is reproduced. An image information reproducing device characterized by restoring and outputting information. 4. Digitize the image information and record it on a recording medium,
In a reproducing device of an image information recording and reproducing system that restores a digital signal reproduced from a recording medium to image information and outputs the image information, if no signal is recorded on the recording medium, at least the effective pixel portion of the reproduced image information is Some or all pixels are set to “0” or “1” for each bit of M-sequence pseudo-random data
An image information reproducing device characterized in that the image information reproducing device replaces and outputs signals corresponding to two types of levels determined in advance. 5. Claims 1, 2, and 3, wherein the replacement of the output signal when no signal is recorded on the recording medium is performed for each predetermined adjacent pixel so that a plurality of predetermined adjacent pixels have the same signal. or 4. The image information reproducing device according to 4. 6. Digitize the image information and record it on a recording medium,
In a playback device of an image information recording and playback system that stores a digital signal reproduced from a recording medium in a memory, reads it out, restores it to image information, and outputs it, if the signal is not recorded on the recording medium, An image information reproducing apparatus characterized in that the read address of the memory is replaced with M-sequence pseudo-random data and the read data is restored to image information and output. 7. According to claim 6, the read address when no signal is recorded on the recording medium is replaced with M-sequence pseudo-random data every predetermined number of times so that the same address is read out a plurality of predetermined times. The image information reproducing device described. 8. Digitize the image information and record it on a recording medium,
In a playback device of an image information recording and playback system that stores a digital signal reproduced from a recording medium in a memory, reads it out, restores it to image information, and outputs it, if the signal is not recorded on the recording medium, An image information reproducing device characterized in that the M-sequence pseudo-random data is subjected to arithmetic operations such as addition, subtraction, multiplication, division, modulo-2 addition, etc. to the readout address of the memory, and the readout data is restored to image information and outputted. 9. When no signal is recorded on the recording medium, the M-series pseudo-random data that is arithmetic operated on the read address is:
9. The image information reproducing apparatus according to claim 8, wherein the image information reproducing apparatus is configured to update the information every predetermined number of times of reading. 10. The image information to be digitized and recorded and reproduced is a composite video signal, and the M-sequence generator for generating the M-sequence pseudo-random data is configured to be initialized every four fields of the video signal. 3, 4, 5, 6, 7, 8
or the image information reproducing device according to 9. 11. After digitizing the image information and encoding it for error detection and correction, and performing error detection and correction on the digital signal recorded and reproduced on the recording medium, add flags to correct uncorrectable errors. In a playback device of an image information recording and playback system that restores and outputs image information through processing such as An image information reproducing device characterized by performing processing. 12. Determine whether or not a signal is recorded on the recording medium based on the playback signal level, and if the playback signal level remains below a predetermined value continuously for a predetermined period of time or more, the signal is recorded. Claims 1, 2, 3, 4, 5, 6, 7, 8, 9 are configured to determine that the
, 10 or 11. 13. Determine whether a signal is recorded on a recording medium by determining whether the reproduced signal conforms to the signal change rules of a predetermined recording modulation method, and determine the frequency at which signals that deviate from the modulation rules appear in the reproduced signal. Claims 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, wherein it is determined that the signal is not recorded when the signal is greater than a predetermined value.
or the image information reproducing device according to item 11. 14. Determine whether or not a signal is recorded on the recording medium based on the detection rate of the synchronization signal included in the reproduced signal, and if the detection rate of the synchronization signal falls below a predetermined value, the signal is recorded. Claim 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 or 1 is configured to determine that the
1. The image information reproducing device according to 1. 15. Whether or not a signal is recorded on the recording medium is determined by the code error rate or uncorrectable error rate detected in the reproduced signal by the error detection or correction code added to the recorded signal, and the value is determined in advance. Claims 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 are configured to determine that the signal is not recorded when the signal exceeds a predetermined value.
or the image information reproducing device according to item 11. 16. Determine whether or not a signal is recorded on the recording medium based on the detection rate in the reproduced signal of an information identification code added to the recorded signal according to a predetermined rule, and determine whether a signal is detected in the reproduced signal in accordance with the rule. Claims 1, 2, 3, 4, 5, 6, 7, wherein it is determined that the signal is not recorded when the number of identification codes in the identification code falls below a predetermined value.
12. The image information reproducing device according to 8, 9, 10 or 11. 17. The reproduced signal is reproduced from the signal recording medium by a plurality of signal reproduction means, and it is determined whether or not a signal is recorded on the recording medium. Claims 1, 2, 3, 4, 5, 6, 7, 8, 9, wherein it is determined that the signal is not recorded on the recording medium when it is determined that the signal is not recorded.
17. The image information reproducing device according to item 10, 11, 12, 13, 14, 15 or 16.