JPH02149153A - Multi-code detecting circuit - Google Patents

Abstract

PURPOSE:To compress a circuit scale by sharing a protection part which detects whether or not the same code is transmitted successively from a various kinds of target codes to be detected. CONSTITUTION:Plural decoders 111 decode specific codes for codes introduced commonly, respectively, and a continuous detecting means 113 judges whether or not the same code exists successively in the codes detected by the plural decoders 111. A protection means 115 decides the transmission of information corresponding to a detected code to the next processing part when the same code is detected successively. Therefore, a system is constituted so that detection information can be outputted only when the same code is detected successively, thereby, the protection part can be shared. In such a way, the circuit can be made into a small scale.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Action Example 1 Correspondence between the Example and FIG. 1■ , Structure of the embodiment ■, Operation of the embodiment ■, Summary of the embodiment ■ 0 Modifications of the invention Effects of the invention [Summary] Concerning a multi-code detection circuit that performs control to determine the next process from a transmitted code , with the aim of reducing the size of the circuit, is to use multiple decoders that each decode a specific code for a commonly introduced code, and a system in which the same code is consecutively detected by multiple decoders. The apparatus is configured to include a continuous detection means for detecting whether or not the same code exists, and a protection means for transmitting information corresponding to the detected code to the next processing section when the same code is detected continuously.

[Industrial application field]

The present invention relates to a multi-code detection circuit, and more particularly, to a multi-code detection circuit that performs subsequent processing control based on a code transmitted through a subscriber transmission line.

(Prior Art) A conventional example is shown in Fig. 4. In the figure, serial data representing various codes is converted into parallel data in a serial-to-parallel conversion circuit 411 consisting of a shift register according to a clock pulse, and then, for example, 3 decoders 4131-413
．． commonly introduced in

Now, suppose that one decoder 4131 decodes, for example, "A" which is the code of "alarm pad". If the introduced code is A, the decoder 413I outputs the decoded alarm information. .Furthermore, each of the other decoders 413□ and 4133 also has its own code B and C.
It decodes the .

The protection circuit 415 (protection circuit 415..415□ and 4153) corresponding to each decoder 413 performs continuous detection processing and calculation processing for the number of transmissions when consecutive detections are made.

For example, each time code A (alarm) continues among the codes indicated by the data, the decoder 413 transmits the decoding information of code A to the protection circuit 415I, and when the protection circuit 415I counts a predetermined number of times, , protection circuit 4151
An output signal is supplied to a detection circuit unit (not shown) connected to the next stage of the code, and the detection circuit unit knows that the code has been reached.

The same applies to the protection circuits 415□ and 4153 connected to the other decoders 413□ and 413:+.

[Problems to be Solved by the Invention] By the way, in the conventional circuit described above, the decoder 41
3, a protection circuit 415 is provided to perform continuous code detection and counting for each code to be detected. J [It was 9fffi. In particular, there is a problem in that the circuit scale becomes larger as the number of codes to be detected increases.

The present invention was created in view of these points, and an object of the present invention is to provide a multi-code detection circuit with a small circuit scale.

[Means to solve the problem]

FIG. 1 is a block diagram showing the principle of a multi-code detection circuit according to the present invention.

In the figure, a plurality of decoders 111 each decode a specific code for commonly introduced codes.

Continuity detection means 113 determines whether or not the same code exists consecutively among the codes detected by the plurality of decoders 111.

When the same code is detected consecutively, the protection means 115 determines to transmit information corresponding to the detected code to the next processing unit.

Therefore, the overall configuration is such that detection information is output only when the same code is detected consecutively.

[For production]

The code represented by the data is sent to multiple decoders 111.
and decoded in either of them.

The decoded code is detected by a continuous detection means 113 to detect whether or not there is a code that appears continuously,
Based on the result, if the same code as the previously detected code is detected, the protection means 115 supplies information corresponding to the detected code to the next processing unit.

In the present invention, since the protection section is shared, the circuit becomes small-scale.

[Example] Hereinafter, an example of the present invention will be described in detail based on the drawings.

FIG. 2 shows the configuration of a multi-code detection circuit in one embodiment of the present invention.

Here, the correspondence relationship between the embodiment of the present invention and FIG. 1 will be shown.

Decoder 111 corresponds to decoders 2211 to 221.

The continuity detection means 113 corresponds to the continuity detection section 231.

The protection means 115 includes a protection circuit 241. and gate 24
Corresponds to 3I-2433.

Examples of the present invention will be described below assuming that the correspondence relationship as described above exists.

The multi-code detection circuit shown in Figure 2 detects three types of codes a,
This detects the continuous transmission of b and c.

In the figure, the multi-code detection circuit according to the embodiment includes a shift register serial-to-parallel conversion circuit 211 that converts serial data representing transmitted codes into parallel data, and three decoders 2211 to 221 that decode the codes. , a continuous detection section 231 that detects whether the same code is transmitted continuously, a protection circuit 241 that protects continuously detected needs, and which detection circuit section (Fig. AND gates 243I-243. It consists of

The continuity detection unit 231 includes continuity detection circuits 233I to 23 that detect whether or not each detection target code is continuously transmitted.
3. , detection transmission circuits 235 to 2353 that hold whether or not the corresponding detection target code has been detected, continuous detection circuits 2331 to 233, and detection transmission circuits 2351 to 2.
Protection target detection circuit 2 determines whether there is a code that is continuously detected in the detection target codes based on the output of 353.
It consists of 37.

Continuous detection circuit 233. ~233. Each of them is composed of one D flip-flop (D-FF) and one AND gate, and the D input terminal of D=FF is connected to the output terminal of the corresponding decoder 221. One input terminal of the AND gate is connected to the output terminal of the corresponding decoder 221, and the other input terminal is connected to the output terminal Q of the D-FF.

Each of the detection transfer circuits 2351 to 2353 has one OR gate and one JK flip-flop (JK-FF).
It is made up of. Each of the two input terminals of the OR gate is connected to each output terminal of two non-corresponding decoders 221.

In addition, the J input terminal of JK-FF is connected to the corresponding decoder 22.
1 and the K input terminal are respectively connected to the output terminal of the OR gate. Here, the detection transmission circuit 23
The input terminals of the OR gate 51 are connected to the decoder 221□ and the decoder 221. The J input terminal of the JK-FF is connected to the output terminal of the decoder 2211.

The protection target detection circuit 237 is composed of four Nant gates. Three Nantes Gates 238, ~238. In each, one input terminal is connected to the corresponding continuous detection circuit 233, and the other input terminal is connected to the output terminal of the detection transfer circuit 235. The other Nantes gates 239 include three Nantes gates 238 . ~2383 outputs are supplied. Also, Nantes Gate 239
The output terminal of is connected to the input terminal of the protection circuit 241.

Each of the controllers 2431 to 2433 has two input terminals, one of which is commonly connected to the output terminal of the protection circuit 241, and the other to the output terminal of the corresponding detection transfer circuit 235.

A clock pulse is introduced into the serial-to-parallel conversion circuit 211, and the clock input terminal T of all D-FF and JK-FF and the clock input terminal T of the protection circuit 241 receives a byte timing pulse as a pulse to measure the timing to take in one byte. Signals have been introduced.

1[-(by Rasaka) The operation of the multi-code detection circuit according to the embodiment of the present invention consists of (1) decoding processing, (2) continuous detection processing, and (2) protection processing. The output values of each circuit are shown when the signal is transmitted as C→C→1)4a.

Note that the code a is sent to the decoder 221. , code b is sent to the decoder 221g, code C is sent to the decoder 221. Assume that each is decoded by Hereinafter, reference will be made to FIGS. 2 and 3. However, it is assumed that all flip-flops are initially in a reset state.

(2) Decoding Process First, data representing a code is converted from a serial state to a parallel state by a serial-to-parallel conversion circuit 211 in accordance with a clock pulse, and then introduced into decoders 2211 to 2213 and decoded. Decoder 22 that performed code detection
1 outputs the logic state "1", and the other decoders 221 output the logic state "0".Here, for the code of a-+a→a→(-+(→b→a) hand,
The output state of the decoder 2211 is 1°°→″1″→u
I II → "°0" → "0°° → "0" → "1". Also, the decoder 221□ changes from "0" → "-〇" → "0"
→“0”→“0”→”“1”→“0′”, decoder 22
1 is 0″→″0″→゛0″→°°1″→“1′→゛°
0” → “0” (see the relevant column in Figure 3).

■Continuous Detection Process Next, the existence of codes that are continuously detected is checked from among all the codes to be detected.

First, continuous detection circuits 2331 to 2 for each detection target code
Check whether the code is detected consecutively in 333,
The detection transmission circuits 2351 to 235° check whether or not a code is detected. A logic state "1" is output from the successive detection circuit 233 in which codes are detected continuously, and a logic state "0" is output from the other detection transmission circuits 235. A logic state "°1" is output from the detection transmission circuit 235 in which the code is detected, and the other detection transmission circuits 235
The logic state °“0” is outputted from.

Next, the continuous detection circuit 233. and detection transfer circuit 2352.
Continuous detection circuit 233□, detection transmission circuit 235□, continuous detection circuit 233. and the two outputs of the detection transfer circuit 2353 respectively to the Nant gates 238, . 23B□ and 2383
By further inputting the outputs of the Nant gates 23EL to 2383 to the Nant gate 239, it is checked whether or not there is one in which the same code is continuously transmitted among all the codes to be detected. Logic state II O11 is output from the Nantes gate 238 where the code is detected continuously, and the logic state ° is output from the other Nantes gates 238.
°1"' is output. If there are consecutively detected codes, the Nant gate 239 outputs the logic state "1".
is output, and if there are no consecutively detected codes, a logic state "0" is output.

As shown in FIG. 3, the first time is code a.

At this time, a continuous detection circuit 233 performs continuous detection of code a.
The output of 1 becomes '0' because the state of the D flip-flop is 0'. The outputs of the other two continuous detection circuits 233□ and 2333 also have the values of each D flip-flop u O
! 1, and the outputs of the decoders 221□ and 2213 are 0'', so it is 0°''.
35. outputs "1", and the detection transfer circuit 235□ and the detection transfer circuit 235. outputs “0”. At this time, Nantes Gate 238. , '23B□ and 2383 are all "1", and the state of Nant Gate 239 is °"
0''. This indicates that there are no consecutively transmitted codes.

Since the second code is also code a, the continuous detection circuit 233. which continuously detects code a. The state of the D flip-flop is "1" and the output state of the decoder 2211 is 1'
Therefore, the output state of the continuous detection circuit 2331 is “1”
°. The value of each D flip-flop of the other continuity detection circuits 233□ and 2333 is 0゛, and the decoder 22
Since the outputs of 12 and 2213 are "0", the output states of the other continuous detection circuits 233□ and 233. are '0°.

It is. At this time, the detection transmission circuit 235. is the logical state “1”
", and the detection transfer circuits 235! and 235. output a logic state "0". In addition, the Nant gate 23B outputs the logic state "0", and the other two Nant gates 23B output the logic state "0".
8□ and 238. Both output the logic state "°I". Therefore, the Nant gate 239 is in the logic state “1”°
, indicating that there are consecutively detected codes.

In this way, the code changes from a to a-+ as shown in Figure 3.
When the signal is transmitted as a→C→C→b→a, the output of the circuit related to code a is determined by the continuity detection circuit 2331 as “0”→
"l'→"1"→"0゛°→"°0"→"0pa→"0゛°, detection transmission circuit 235. is “1” → “I II → II
I II→“O”→610”→“0”→“0”, Nantes Gate 2381 is “°1”→”OII→“°0°°→
"1"→"l"→°"1゛°→°"1n.

The output of the circuit related to code b is the continuity detection circuit 233
゜ is 0” → “0” → “0” → “0” → II OII → “
0°'→“0”, detection transfer circuit 235° is “0”→°゛0″→°“0”→″0″→“0”→1″→“0”, Nant gate 2382 is “1” →″１″→″I II→″l
"→"l"→"1"→"1".

The output of the circuit related to code C is the continuity detection circuit 233.
3 is “0” → “0” →, “0” → “0” → 111” → “
0"→"0"°, detection transfer circuit 235° is II OH→
II O”→“0”→″11′→II 1”→0°°→
“0”, Nantes Gate 238. is “1” → “1” → “1”
′→“+1+1→“0”→“1”→“1”.

As a result, the state of the Nant gate 239 is 0°゛→″1″
→"1"→"0"→II 1"→II O"→0".

■Protection processing If there are codes detected continuously (Nantes Gate 2
When the output of the Nant gate 239 is in the logic state "1"), the output logic state of the protection circuit 241 is "1". 0”), the protection circuit 24
The output logic state of 1 becomes "0". This protection circuit 241
The output of AND gate 243. ~243. Since the continuous detection code is supplied in common to both, the continuous detection code is specified depending on which AND gate 243 is passed through. In other words, when the logic state of the protection circuit 241 is "1", the AND gate 243 corresponding to the decoder that detected the code outputs the logic state "1°", and the other AND gates 243 output "0". Output.

As shown in Figure 3, the code is a-4a→a→C→c-
When +b-+a is transmitted, the output state of the protection circuit 241 is '0゛→“'1°”→゛1”→“0゛→°“l I
I→゛0°゛→II OII, in which case Antogame)243. is “°0”→II I H→”1゛°→”
0''→“0°'→“0”→”Outputs “0”. Also, the state of the AND gate 243□ is “0゛°→°“0゛→“
0゛° → uO” → “0” → “0” → “0”, code b
indicates that they were not transmitted consecutively.

The state of Antogame) 243+ is °“0”→“0”→“
0''→“0゛°→“1”→°′0”→′°0′”.

ANDGATE 2431-243. The output results are transmitted to the respective detection circuit sections, and the AND gates 2431 to 24
3. The next process is determined according to "1'' in the output result of .

■ Focusing on the point that two or more input codes do not occur at the same time, the protection part that detects whether or not the same code is continuously transmitted from a variety of detection target codes is shared. Therefore, small-scale circuits can be realized.

■ No. 1 In the embodiment of the present invention described above, rear protection was taken up, but in the case of forward protection, the J input terminal of the JK-FF is masked so that even if other codes are transmitted, JK-FF
so that the results do not change.

Furthermore, there may be four or more types of codes to be detected.

In this case, the decoder 221 continuity detection circuit 233 . Detection transfer circuit 235. Nanto Game) 238
．． An AND gate 243 may be provided.

Furthermore, in "1. Correspondence between Examples and FIG. 1",
- Although the correspondence between the present invention and the embodiments has been explained, those skilled in the art will easily guess that the present invention is not limited to this and that there are various modifications.

[Effects of the Invention] As described above, according to the present invention, since the continuous detection portion of code transmission is shared, the circuit scale is reduced and it is extremely useful in practice.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of a multi-code detection circuit according to the present invention; FIG. 2 is a block diagram of the configuration of a multi-code detection circuit according to an embodiment of the present invention; FIG. 3 is an explanatory diagram of output values of each circuit; FIG. 4 is an explanatory diagram of the prior art. In the figure, 111 is a decoder, 113 is a continuity detection means, 115 is a protection means, 211.411 is a serial-to-parallel conversion circuit, 221.413 is a decoder, 231 is a continuity detection section, 233 is a continuity detection circuit, 235 is a detection transmission 237 is a protection target detection circuit, 238.239 is a Nant gate, 241.415 is a protection circuit, and 243 is an AND gate. Embryo East Shake ( , Sai 5.
Figure 3

Claims (1)

[Claims] (1) A plurality of decoders (111) each decoding a specific code for a commonly introduced code, and the same code exists consecutively among the codes detected by the plurality of decoders (111). continuous detection means (113) for detecting whether the same code is detected consecutively; and protection means (115) for determining to transmit information corresponding to the detected code to the next processing unit when the same code is detected continuously. What is claimed is: 1. A multi-code detection circuit comprising: