JPH0215033B2 - - Google Patents
Info
- Publication number
- JPH0215033B2 JPH0215033B2 JP57078561A JP7856182A JPH0215033B2 JP H0215033 B2 JPH0215033 B2 JP H0215033B2 JP 57078561 A JP57078561 A JP 57078561A JP 7856182 A JP7856182 A JP 7856182A JP H0215033 B2 JPH0215033 B2 JP H0215033B2
- Authority
- JP
- Japan
- Prior art keywords
- drive
- voltage
- transistor
- resistor
- driver
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Power Conversion In General (AREA)
- Dot-Matrix Printers And Others (AREA)
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
Description
【発明の詳細な説明】
(a) 発明の技術分野
本発明はドツトプリンタの印字ピン駆動部（ド
ライバ）の異常を検知するドライバチエツク回路
に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a driver check circuit for detecting an abnormality in a print pin drive section (driver) of a dot printer.
(b) 従来技術と問題点
印字ピンの駆動により印字を行うドツトプリン
タは多数のマグネツト駆動回路を有する。このマ
グネツト駆動回路の構成素子であるトランジスタ
の破壊、又はマグネツトコイルのシヨート（対フ
レーム）等を生じた場合には、マグネツトやコイ
ルや駆動素子の焼損や発煙を生ずる。この発生を
検知する手段としては各マグネツトドライバ（ト
ランジスタ）の駆動出力電圧をチエツクする方法
が採用されており、この従来方式を図によつて説
明する。第１図は従来方式を説明する回路図であ
り、１はチエツク回路、２はコンパレータ、３は
カウンタ、A1，A2，Aoは駆動信号、b1，b2，bo
は入力端子、Ｃはコンデンサ、D1，D2，Doはダ
イオード、Ｅ，Ｖは供給電圧、I1，I2，Ioはイン
バータ、L1，L2，Loは駆動コイル（マグネツト
コイル）、Q1，Q2，Qoはドライバ、R0，r1，r2，
r3，r4，roは抵抗器、Ｓは制御信号、VRは基準電
圧である。第１図における入力端子b1〜boに駆動
信号A1〜Aoが入力されることによりドライバQ1
〜QoがONとなり、駆動コイルL1〜Loに駆動電流
が流されて印字ピン（図示していない）が駆動さ
れ、印字が行われる。このような駆動回路におい
て、駆動コイルL1〜Loがシヨート（対フレーム）
したり、ドライバQ1〜Qoに異常を生じた場合、
発熱、発煙を生じ、遂には駆動コイルや素子の焼
損・破壊に至る。このような異常の発生を検知す
る手段としてチエツク回路１とカウンタ３を設
け、マグネツト駆動時のドライバQ1〜Qoと駆動
コイルL1〜Loとの接続点の電圧の低下を監視し
ており、この低下状態の持続時間が正常な駆動時
間に対して異常に長いかどうかを、カウンタ３で
クロツクパルスをカウントすることにより時間監
視してチエツクしているが、従来方式では検出手
段としてチエツク回路１は、基準電圧VRとコン
パレータ２とを備え、各ドライバと駆動コイルと
の接続点の電圧を基準電圧と比較して検出するよ
うになつており、更にマグネツトが複数のため、
ドライバと駆動コイルの各対間の干渉（回り込
み）を防止するためのダイオードD1〜Doによる
OR回路を備えており複雑で高価となる欠点があ
つた。(b) Prior Art and Problems A dot printer that prints by driving a printing pin has a large number of magnet drive circuits. If a transistor, which is a component of the magnet drive circuit, is destroyed or the magnet coil is shot (to the frame), the magnet, coil, or drive element will burn out and smoke will occur. A method of checking the drive output voltage of each magnet driver (transistor) is adopted as a means for detecting this occurrence, and this conventional method will be explained with reference to the drawings. FIG. 1 is a circuit diagram explaining the conventional system, where 1 is a check circuit, 2 is a comparator, 3 is a counter, A 1 , A 2 , A o are drive signals, b 1 , b 2 , b o
is an input terminal, C is a capacitor, D 1 , D 2 , Do are diodes, E, V are supply voltages, I 1 , I 2 , I o are inverters, L 1 , L 2 , Lo are drive coils (magnets), net coil), Q 1 , Q 2 , Q o are drivers, R 0 , r 1 , r 2 ,
r 3 , r 4 , r o are resistors, S is a control signal, and V R is a reference voltage. When drive signals A 1 to A o are input to input terminals b 1 to b o in FIG. 1 , the driver Q 1
~Q o is turned ON, a drive current is passed through the drive coils L 1 ~ L o , a printing pin (not shown) is driven, and printing is performed. In such a drive circuit, the drive coils L 1 to L o are short (toward the frame)
or if an abnormality occurs in drivers Q 1 to Q o ,
This generates heat and smoke, eventually leading to burnout and destruction of the drive coil and elements. As a means for detecting the occurrence of such an abnormality, a check circuit 1 and a counter 3 are provided to monitor the drop in voltage at the connection point between the drivers Q 1 -Q o and the drive coils L 1 -L o during magnet drive. Therefore, whether the duration of this reduced state is abnormally long compared to the normal driving time is checked by monitoring the clock pulses with the counter 3, but in the conventional method, a check circuit is used as a detection means. 1 is equipped with a reference voltage V R and a comparator 2, and is designed to detect the voltage at the connection point between each driver and the drive coil by comparing it with the reference voltage.Furthermore, since there are multiple magnets,
By diodes D 1 to D o to prevent interference (wrapping) between each pair of driver and drive coil
It had the disadvantage of being complicated and expensive because it had an OR circuit.
(c) 発明の目的
本発明は上記の欠点を解決するためになされた
もので、基準電圧とコンパレータとを用いること
もなく、またダイオードOR回路を用いなくとも
済むドライバチエク回路の提供を目的とする。(c) Purpose of the Invention The present invention has been made to solve the above-mentioned drawbacks, and an object of the present invention is to provide a driver check circuit that does not use a reference voltage, a comparator, or a diode OR circuit. .
(d) 発明の構成
本発明は、電圧Ｖの電源に一端を接続したマグ
ネツト駆動コイルの他端とアースとの間に駆動素
子を接続し、該駆動素子に駆動信号を与えること
により前記駆動コイルに通電して前記マグネツト
を駆動するドライバ回路において、前記駆動コイ
ルと駆動素子との接続点に第１の抵抗を介してベ
ースを接続し、前記電源にエミタを接続し、コレ
クタを負荷抵抗を介してアースに接続し、該コレ
クタの電圧をチエツク出力とするトランジスタを
設けると共に、該トランジスタのベースを第２の
抵抗を介して前記電源に接続し、前記駆動コイル
と駆動素子との接続点の電圧であつて前記ドライ
バ回路の駆動状態を検出する電圧をVCとし、前
記第１、第２の抵抗を夫々R1，R2とし、前記ト
ランジスタのしきい値電圧をVTとする時
（Ｖ−VC）×R2／（R1＋R2）＞VT
なる条件を満足するようにR1，R2を定めること
を特徴とするドライバチエツク回路である。(d) Structure of the Invention The present invention provides a magnetic drive coil having one end connected to a power source of voltage V, and a drive element connected between the other end of the magnetic drive coil and the ground, and applying a drive signal to the drive element. In the driver circuit for driving the magnet by supplying current to the magnet, the base is connected to the connection point between the drive coil and the drive element via a first resistor, the emitter is connected to the power supply, and the collector is connected to the connection point between the drive coil and the drive element via a load resistor. A transistor is provided which is connected to the ground and whose collector voltage is a check output, and whose base is connected to the power supply via a second resistor to check the voltage at the connection point between the drive coil and the drive element. When the voltage for detecting the driving state of the driver circuit is V C , the first and second resistors are R 1 and R 2 , respectively, and the threshold voltage of the transistor is V T , (V This driver check circuit is characterized in that R 1 and R 2 are determined so as to satisfy the condition: -V C )×R 2 /(R 1 +R 2 )>V T .
(e) 発明の実施例
以下、本発明を図面によつて説明する。第２図
は本発明の一実施例を説明する回路図であり、
１′はチエツク回路、CPはクロツクパルス、I3，
I4はインバータ、Ｐはプリセツト信号、R11，
R12，R1o，R2，R3，R4，R5は抵抗、Ｓは制御信
号、Ｔ，Trはトランジスタ、VCは駆動コイルL1
〜Loと駆動素子ドライバ即ちトランジスタQ1〜
Qoとの接続点の電圧であつて、各ドライバ回路
の駆動状態を検出するための所定電圧であり、そ
の他の記号は第１図と同一である。第２図におい
てトランジスタTrは検出用トランジスタであり、
その入力端（ベース）は、抵抗R11〜R1oを介し
てドライバQ1〜Qoのコレクタに結ばれている。
またトランジスタTrのエミツタとベースとの間
に抵抗R2を設ける。(e) Examples of the invention The present invention will be explained below with reference to the drawings. FIG. 2 is a circuit diagram illustrating an embodiment of the present invention,
1' is a check circuit, CP is a clock pulse, I 3 ,
I 4 is an inverter, P is a preset signal, R 11 ,
R 12 , R 1o , R 2 , R 3 , R 4 , R 5 are resistances, S is a control signal, T and Tr are transistors, and V C is a drive coil L 1
~ Lo and driving element driver, i.e. transistor Q1 ~
This is the voltage at the connection point with Qo , and is a predetermined voltage for detecting the driving state of each driver circuit.Other symbols are the same as in FIG. In FIG. 2, the transistor Tr is a detection transistor,
Its input end (base) is connected to the collectors of the drivers Q1 to Qo via resistors R11 to R1o .
Further, a resistor R2 is provided between the emitter and base of the transistor Tr.
抵抗R11〜R1oは同値であるから抵抗R1iで代表
し、トランジスタTr（バイポーラ）のしきい値電
圧をVTとしたとき、抵抗R2と抵抗R1iは、
（Ｖ−VC）×R2／（R1i＋R2）＞VT
を満足するように設定する。 Since the resistors R 11 to R 1o have the same value, they are represented by the resistor R 1i , and when the threshold voltage of the transistor Tr (bipolar) is V T , the resistors R 2 and R 1i are (V-V C ) Set so that ×R 2 / (R 1i + R 2 ) > V T is satisfied.
尚、しきい値電圧VTは、シリコンの場合は約
0.7ボルトであり、例えば供給電圧Ｖ＝24ボルト
の場合には抵抗R2の電圧降下が0.7ボルト以上に
なつたときに、トランジスタTrがONとなる。通
常マグネツトは複数ｎ個であり、各ドライバQ1
〜Qoと各駆動コイルL1〜Loとの夫々の接続点は
複数ｎ個となりこれらの点が抵抗R1iを介してト
ランジスタTrのベースに並列に接続されるので、
各ドライバの駆動の回り込み（干渉）を防止する
必要があり、抵抗R1iは10Kオーム以上に定める。 In addition, the threshold voltage V T is approximately
For example, when the supply voltage V=24 volts, the transistor Tr turns on when the voltage drop across the resistor R2 becomes 0.7 volts or more. Usually there are a plurality of n magnets, each driver Q 1
There are a plurality of n connection points between ~Q o and each drive coil L 1 ~ L o , and these points are connected in parallel to the base of the transistor Tr via the resistor R 1i .
It is necessary to prevent the drive of each driver from running around (interference), and the resistance R 1i is set to 10K ohms or more.
VCはＶに比較的近い高電圧まで検出すること
が望ましく、所望に定めたVCと定められた抵抗
Ri1とを前記の式に代入することにより抵抗R2を
決定することが出来る。 It is desirable to detect V C up to a high voltage relatively close to V, and it is desirable to detect V C up to a high voltage that is relatively close to V.
By substituting R i1 into the above equation, the resistance R 2 can be determined.
一方、このように抵抗R1iを高抵抗にすると、
トランジスタTrのベースとアースとの間に容量
（コンデンサ、図示省略）を追加して、この容量
と各抵抗R1iによるノイズ防止の積分回路も構成
可能である。ドライバQ1〜Qoの破壊又は駆動コ
イルL1〜Loのシヨート（対フレーム）を生じた
場合には、抵抗R11〜R1oを介してトランジスタ
Trのベース電位が低くなり、トランジスタTrが
ONとなる。従つてコレクタ負荷である抵抗器R3
に出力電位が現われ、抵抗R4を介してトランジ
スタＴに入力される。 On the other hand, if the resistance R 1i is made high in this way,
By adding a capacitor (capacitor, not shown) between the base of the transistor Tr and the ground, it is also possible to configure an integration circuit for noise prevention using this capacitor and each resistor R 1i . If the drivers Q 1 to Q o are destroyed or the drive coils L 1 to L o are shorted (to the frame), the transistors are connected via the resistors R 11 to R 1o .
The base potential of Tr becomes low, and the transistor Tr becomes
It becomes ON. Resistor R 3 which is therefore the collector load
An output potential appears at and is input to the transistor T via the resistor R4 .
その出力はインバータI3を介してリセツト信号
Ｐとなつてカウンタ３へ送出される。ここでR4，
Ｔ，R5はTrの出力をTTLレベルに変換するレベ
ル変換回路路である。リセツト信号Ｐが“Ｈ”と
なるとカウンタ３はクロツクパルスCPのカウン
トを開始し、フルカウントで（予め端子P0、P1、
P2、P3への指定入力によつて設定されているカ
ウントの上限値までカウントして）、この場合異
常検出信号である制御信号Ｓを送出する。一方、
制御信号Ｓによりカウントイネーブル端子を
OFFとし以降のカウンントを禁止するようにな
つている。 The output is sent to the counter 3 via the inverter I3 as a reset signal P. Here R 4 ,
T, R5 is a level conversion circuit that converts the output of the Tr to a TTL level. When the reset signal P becomes "H", the counter 3 starts counting the clock pulses CP, and at a full count (terminals P0, P1,
(up to the upper limit of the count set by the specified input to P2 and P3), and in this case a control signal S, which is an abnormality detection signal, is sent out. on the other hand,
Count enable terminal is activated by control signal S.
It is now set to OFF and subsequent counting is prohibited.
カウンタ３のクロツクパルスCPのフルカウン
トに対応する時間は、ドライバQ1〜Qoによる各
駆動コイルL1〜Loの正常動作での通電時間はよ
り長く設定されており、正常動作ではフルカウン
トに達する前にリセツト信号Ｐが“Ｌ”となりカ
ウンタ３ははリセツトされるので異常検出信号
（制御信号Ｓ）が送出されることはないようにな
つている。 The time corresponding to the full count of the clock pulse CP of the counter 3 is set longer than the energization time in normal operation of each drive coil L 1 to L o by the drivers Q 1 to Q o , and the time corresponding to the full count of the clock pulse CP of the counter 3 is set longer than that in normal operation. Since the reset signal P becomes "L" and the counter 3 is reset, the abnormality detection signal (control signal S) is not sent out.
(f) 発明の効果
以上のように本発明は、検出手段にコンパレー
タや基準電圧を必要とせず、更にダイオードを抵
抗に替えて回路を簡単且つ安価にする効果があ
り、また、その抵抗をノイズ防止の積分回路の素
子に利用できる利点を有する。(f) Effects of the Invention As described above, the present invention does not require a comparator or a reference voltage as a detection means, and also has the effect of making the circuit simpler and cheaper by replacing the diode with a resistor. It has the advantage that it can be used as an element of a prevention integration circuit.
第１図は従来方式を説明する回路図、第２図は
本発明の一実施例を説明する回路図であり、図中
に用いた符号は次の通りである。
１，１′はチエツク回路、２はコンパレータ、
３はカウンタ、A1は駆動信号、b1，b2，boは入
力端子、Ｃはコンデンサ、CPはクロツクパルス、
D1，D2，Doはダイオード、Ｅ，Ｖは供給電圧、
I1，I2，I3，I4，Ioはインバータ、L1，L2，Loは駆
動コイル、Ｐ，P0，P1，P2，P3はプリセツト信
号、Q1，Q2，Qoはドライバ、R0，r1，r2，r3，
r4，ro，R11，R12，R1o，R2，R3，R4，R5は抵抗
器、Ｓは制御信号、Ｔ，Trはトランジスタ、Ｖ
は供給電圧、VCはコレクタ電圧、VRは基準電圧
を示す。
FIG. 1 is a circuit diagram illustrating a conventional system, and FIG. 2 is a circuit diagram illustrating an embodiment of the present invention. Reference symbols used in the figures are as follows. 1 and 1' are check circuits, 2 is a comparator,
3 is a counter, A 1 is a drive signal, b 1 , b 2 , b o are input terminals, C is a capacitor, CP is a clock pulse,
D 1 , D 2 , D o are diodes, E, V are supply voltages,
I 1 , I 2 , I 3 , I 4 , I o are inverters, L 1 , L 2 , Lo are drive coils, P, P 0 , P 1 , P 2 , P 3 are preset signals, Q 1 , Q 2 , Q o is the driver, R 0 , r 1 , r 2 , r 3 ,
r 4 , r o , R 11 , R 12 , R 1o , R 2 , R 3 , R 4 , R 5 are resistors, S is a control signal, T and Tr are transistors, V
is the supply voltage, V C is the collector voltage, and V R is the reference voltage.
Claims (1)
動コイルの他端とアースとの間に駆動素子を接続
し、該駆動素子に駆動信号を与えることにより前
記駆動コイルに通電して前記マグネツトを駆動す
るドライバ回路において、 前記駆動コイルと駆動素子との接続点に第１の
抵抗を介してベースを接続し、前記電源にエミタ
を接続し、コレクタを負荷抵抗を介してアースに
接続し、該コレクタの電圧をチエツク出力とする
トランジスタを設けると共に、該トランジスタの
ベースを第２の抵抗を介して前記電源に接続し、 前記駆動コイルと駆動素子との接続点の電圧で
あつて前記ドライバ回路の駆動状態を検出する電
圧をVCとし、前記第１、第２の抵抗を夫々R1，
R2とし、前記トランジスタのしきい値電圧をVT
とする時 （Ｖ−VC）×R2／（R1＋R2）＞VT なる条件を満足するようにR1，R2を定めること
を特徴とするドライバチエツク回路。[Claims] 1. A drive element is connected between the other end of a magnetic drive coil whose one end is connected to a power source of voltage V and the ground, and a drive signal is applied to the drive element to energize the drive coil. In the driver circuit for driving the magnet, a base is connected to a connection point between the drive coil and the drive element via a first resistor, an emitter is connected to the power source, and a collector is connected to ground via a load resistor. A transistor is connected and the voltage at the collector is checked as output, and the base of the transistor is connected to the power supply via a second resistor, and the voltage at the connection point between the drive coil and the drive element is The voltage for detecting the drive state of the driver circuit is V C , and the first and second resistors are R 1 and R 1 , respectively.
R 2 and the threshold voltage of the transistor is V T
A driver check circuit characterized in that R 1 and R 2 are determined so as to satisfy the following condition: (V-V C )×R 2 /(R 1 +R 2 )>V T .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57078561A JPS58195470A (en) | 1982-05-11 | 1982-05-11 | Driver checking circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57078561A JPS58195470A (en) | 1982-05-11 | 1982-05-11 | Driver checking circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58195470A JPS58195470A (en) | 1983-11-14 |
| JPH0215033B2 true JPH0215033B2 (en) | 1990-04-10 |
Family
ID=13665314
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57078561A Granted JPS58195470A (en) | 1982-05-11 | 1982-05-11 | Driver checking circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58195470A (en) |
-
1982
- 1982-05-11 JP JP57078561A patent/JPS58195470A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58195470A (en) | 1983-11-14 |
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