JPH02152243A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH02152243A
JPH02152243A JP63306336A JP30633688A JPH02152243A JP H02152243 A JPH02152243 A JP H02152243A JP 63306336 A JP63306336 A JP 63306336A JP 30633688 A JP30633688 A JP 30633688A JP H02152243 A JPH02152243 A JP H02152243A
Authority
JP
Japan
Prior art keywords
terminal
semiconductor chip
pole
external terminal
terminal piece
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63306336A
Other languages
Japanese (ja)
Other versions
JP2510708B2 (en
Inventor
Shigemasa Sunada
重政 砂田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP63306336A priority Critical patent/JP2510708B2/en
Publication of JPH02152243A publication Critical patent/JPH02152243A/en
Application granted granted Critical
Publication of JP2510708B2 publication Critical patent/JP2510708B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07353—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/076—Connecting or disconnecting of strap connectors
    • H10W72/07651—Connecting or disconnecting of strap connectors characterised by changes in properties of the strap connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/331—Shapes of die-attach connectors
    • H10W72/334—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/60—Strap connectors, e.g. thick copper clips for grounding of power devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/60—Strap connectors, e.g. thick copper clips for grounding of power devices
    • H10W72/631—Shapes of strap connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ダイオード等のように、一つの半導体チップ
に対して二本の外部端子を接続したいわゆる二端子型の
半導体装置に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a so-called two-terminal type semiconductor device, such as a diode, in which two external terminals are connected to one semiconductor chip. .

〔従来の技術〕[Conventional technology]

従来におけるダイオード等のような二端子型半導体装置
は、第２０図乃至第２２図に示すように、一つの半導体
チップｌを、金属板に形成された二枚の外部端子２，３
における端子片２ａ、３ａの間に挿入したのち、該半導
体チップ１におけるＮ極１ａの下面に、一方の外部端子
２における端子片２ａを、半田等の金ＲＭＪろう材４に
て接合する一方、半導体チップ１におけるＰ極１ｂの上
面に、他方の外部端子３における端子片３ａを、同じく
半田等の金Ｂ１１ろう材５にて接合したのち、その全体
を合成樹脂のモールＦ部６により密封するように構成し
ていることは周知の通りである。A conventional two-terminal semiconductor device such as a diode, as shown in FIGS. 20 to 22, connects one semiconductor chip l to two external terminals 2 and 3 formed on a metal plate.
After inserting the terminal piece 2a between the terminal pieces 2a and 3a in the semiconductor chip 1, the terminal piece 2a of one external terminal 2 is bonded to the lower surface of the N-pole 1a of the semiconductor chip 1 with gold RMJ brazing material 4 such as solder, After bonding the terminal piece 3a of the other external terminal 3 to the top surface of the P pole 1b of the semiconductor chip 1 using a gold B11 brazing material 5 such as solder, the whole is sealed with a synthetic resin molding F part 6. It is well known that the system is configured as follows.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし、従来の二端子型半導体装置では、他方の外部端
子３における端子片３ａを、半導体チップ１よりも大き
い寸法にし、該端子片３ａを、半導体チップ１における
Ｐ極１ｂの上面に対して、半田等の金属製ろう材５にて
接合する構成にしている。However, in the conventional two-terminal semiconductor device, the terminal piece 3a of the other external terminal 3 is made larger than the semiconductor chip 1, and the terminal piece 3a is placed against the upper surface of the P pole 1b of the semiconductor chip 1. The structure is such that they are joined using a metal brazing material 5 such as solder.

このため、半導体チップ１におけるＰ極１ｂの上面に対
して端子片３ａを、その間に供給したろう材６によって
接合する場合において、溶融したろう材５のうち余剰の
ろう材５ａが、前記端子片３ａの下面に沿ってＰ極１ｂ
の外側の部位まで広がったのち、半導体チップ１の外側
面に沿って垂れ下がる傾向を呈するものであるから、前
記の接合工程中において、熔融ろう材５のうち余剰のろ
う材５ａが、半導体チンプ１においてＰ極１ｂとＮ極１
ａとの接合周囲を被覆する保護膜ＩＣを越えて大きく垂
れ下がって、半導体チップｌにおけるＮ＋ｉｌａに接合
すると云う事態が発生するのであり、前記ろう材５の、
垂れ下がりによる不良品の発生率が高いのであった。Therefore, when the terminal piece 3a is bonded to the upper surface of the P pole 1b in the semiconductor chip 1 with the brazing filler metal 6 supplied therebetween, the excess brazing filler metal 5a of the melted brazing filler metal 5 is transferred to the terminal piece. P pole 1b along the lower surface of 3a
After spreading to the outer part of the semiconductor chip 1, it tends to hang down along the outer surface of the semiconductor chip 1. Therefore, during the above bonding process, the excess brazing filler metal 5a of the molten brazing filler metal 5 spreads to the outside of the semiconductor chip 1. P pole 1b and N pole 1 in
A situation occurs in which the soldering material 5 hangs down greatly beyond the protective film IC covering the area around the bonding material 5, and is bonded to N+ila in the semiconductor chip 1.
The incidence of defective products due to sagging was high.

本発明は、この問題を解消した半導体装置を提供するも
のである。The present invention provides a semiconductor device that solves this problem.

〔課題を解決するための手段〕[Means to solve the problem]

この目的を達成するため請求項１は、半導体チップを、
金属板で形成された二枚の外部端子における端子片の間
に挿入し、該半導体チップにおける一方の極の下面に、
一方の外部端子における端子片を、半導体チップにおけ
る他方の掻の上面に、他方の外部端子における端子片を
、各々ろう材にて接合して成る半導体装置において、前
記他方の外部ｎｊ子における端子片に、半導体チップの
他方の極における上面のうち一部の上面を露出するよう
にした切欠部を設ける構成にした。To achieve this object, claim 1 provides a semiconductor chip comprising:
It is inserted between the terminal pieces of two external terminals formed of metal plates, and on the lower surface of one pole of the semiconductor chip,
In a semiconductor device in which a terminal piece of one external terminal is bonded to the upper surface of the other side of the semiconductor chip, and a terminal piece of the other external terminal is bonded to the top surface of the other external terminal using brazing material, the terminal piece of the other external terminal is bonded to the top surface of the other external terminal of the semiconductor chip. In this case, a cutout portion is provided to expose a part of the upper surface of the other pole of the semiconductor chip.

また、請求項２は、半導体チップを、金属板で形成され
た二枚の外部端子における端子片の間に挿入し、該半導
体チップにおける一方の極の下面に、一方の外部端子に
おける端子片を、半導体チップにおける他方の極の上面
に、他方の外部端子における端子片を、各々ろう材にて
接合して成る半導体装置において、前記他方の外部端子
における端子片に、半導体チップの他方の極における上
面のうち一部の上面を露出するようにした抜き孔を設け
る構成にした。In addition, in claim 2, a semiconductor chip is inserted between terminal pieces of two external terminals formed of metal plates, and the terminal piece of one external terminal is placed on the lower surface of one pole of the semiconductor chip. , in a semiconductor device in which a terminal piece of the other external terminal is bonded to the upper surface of the other pole of the semiconductor chip with a brazing material, the terminal piece of the other external terminal is bonded to the top surface of the other pole of the semiconductor chip; A punch hole is provided to expose a part of the upper surface.

更にまた、請求項３は、半導体チップを、金属板で形成
された二枚の外部端子における端子片の間に挿入し、該
半導体チップにおける一方の極の下面に、一方の外部端
子における端子片を、半導体チップにおける他方の極の
上面に、他方の外部端子における端子片を、各々ろう材
にて接合して成る半導体装置において、前記他方の外部
端子における端子片の幅寸法及び長さ寸法のうちいずれ
か一方又は両方を、半導体チップの他方の極における上
面の一部が露出するように短（又は狭くする構成にした
。Furthermore, a third aspect of the present invention provides that the semiconductor chip is inserted between the terminal pieces of two external terminals formed of metal plates, and the terminal piece of one external terminal is placed on the lower surface of one pole of the semiconductor chip. In a semiconductor device in which a terminal piece of the other external terminal is bonded to the top surface of the other pole of the semiconductor chip using a brazing material, the width and length of the terminal piece of the other external terminal are One or both of them are shortened (or narrowed) so that a part of the upper surface of the other pole of the semiconductor chip is exposed.

〔発明の作用・効果〕[Action/effect of the invention]

前記請求項１のように構成すると、半導体チップにおけ
る他方の極の上面に対して、他方の外部端子における端
子片を、その間に供給した溶融ろう材によって接合する
に際して、前記溶融ろう材のうち余剰のものは、他方の
外部端子における端子片に設けた切欠部内の箇所に集ま
り、当該箇所に、表面張力によって盛り上がることにな
るから、余剰の溶融ろう材が、半導体チップの外側面に
向って大きく垂れ下がることを、確実に防止できて、ろ
う材の垂れ下がりによる不良品の発生率を低減できるの
である。According to the first aspect, when the terminal piece of the other external terminal is bonded to the upper surface of the other pole of the semiconductor chip using the molten brazing material supplied therebetween, the excess of the molten brazing material is removed. The excess molten brazing material gathers in the notch provided in the terminal piece of the other external terminal, and swells up at that location due to surface tension, causing excess molten brazing material to move toward the outside surface of the semiconductor chip. It is possible to reliably prevent the brazing filler metal from sagging, and reduce the incidence of defective products due to the brazing filler metal sagging.

また、前記請求項２のように構成すると、熔融ろう材の
余剰のものは１．他方の外部端子における端子片に設け
た抜き孔内に集まり、当該抜き孔内に盛り上がることに
なって、余剰の溶融ろう材が、半導体チップの外側面に
向って大きく垂れ下がることを、確実に防止できるから
、ろう材の垂れ下がりによる不良品の発生率を低減でき
るのである。Moreover, when configured as in claim 2, the excess melted brazing material is reduced to 1. This method reliably prevents excess molten brazing material from gathering in the hole provided in the terminal piece of the other external terminal and rising inside the hole, thereby preventing excessive molten brazing material from greatly hanging down toward the outer surface of the semiconductor chip. This makes it possible to reduce the incidence of defective products due to brazing filler metal sagging.

更にまた、前記請求項３のように構成すると、溶融ろう
材の余剰のものは、半導体チップにおける他方の極の上
面のうち、他方の外部端子における端子片より露出する
部分に集まり、当該部分に、表面張力によって盛り上が
ることになるから、余剰のン容融ろう材が、半導体チッ
プの外側面に向って大きく垂れ下がることを、確実に防
止できて、ろう材の垂れ下がりによる不良品の発生率を
低減できるのである。Furthermore, with the structure according to claim 3, the surplus of the molten brazing material collects on the upper surface of the other pole of the semiconductor chip at the part exposed from the terminal piece of the other external terminal, and , since it swells due to surface tension, it is possible to reliably prevent excess brazing filler metal from drooping significantly toward the outside surface of the semiconductor chip, reducing the incidence of defective products due to sagging brazing filler metal. It can be done.

〔実施例〕〔Example〕

以下、本発明の実施例を図面について説明する。 Embodiments of the present invention will be described below with reference to the drawings.

第１図乃至第３図は、前記請求項１に対する第１の実施
例を示し、この図において符号１は、Ｎ極１ａと、Ｐ極
１ｂとを有する半導体チ・ノブを、符号２は、全屈板製
の一方の外部端子を、符号３は、同じく全屈板製の他方
の外部端子を各々示し、前記一方の外部端子２には、幅
寸法Ｓ１及び長さ寸法Ｌ１を、前記半導体チップ１にお
ける幅寸法Ｓ及び長さ寸法りよりも大きくした端子片２
ａが形成され、また、前記他方の外部端子３にも、幅寸
法Ｓ２及び長さ寸法Ｌ２を、前記半導体チ・ノブ１にお
ける幅寸法Ｓ及び長さ寸法りよりも大きくした端子片３
ａが形成されている。1 to 3 show a first embodiment of claim 1, in which reference numeral 1 denotes a semiconductor chip knob having an N pole 1a and a P pole 1b; Reference numeral 3 indicates one external terminal made of a fully bent plate, and reference numeral 3 indicates the other external terminal also made of a fully bent plate. Terminal piece 2 larger than width dimension S and length dimension in chip 1
a is formed, and the other external terminal 3 also has a terminal piece 3 having a width S2 and a length L2 larger than the width S and length L2 of the semiconductor chip knob 1.
a is formed.

前記半導体チップ１におけるＮ極１ａの下面に、前記一
方の外部端子２における端子片２ａを、半田等のろう材
４によって接合する。The terminal piece 2a of the one external terminal 2 is bonded to the lower surface of the N-pole 1a of the semiconductor chip 1 using a brazing material 4 such as solder.

τ方、前記半導体チップ１におけるＰ極１ｂの上面に、
前記他方の外部端子３における端子片３ａを、同じく半
田等のろう材４によって接合するに際して、前記他方の
外部端子３における端子片３ａに、長溝状の切欠部７を
設ける。On the τ side, on the upper surface of the P pole 1b in the semiconductor chip 1,
When the terminal piece 3a of the other external terminal 3 is similarly bonded with a brazing material 4 such as solder, a long groove-shaped notch 7 is provided in the terminal piece 3a of the other external terminal 3.

すると、半導体チップ１におけるＰ極１ｂの上面に対し
て、他方の外部端子３における端子片３ａを、その間に
供給した溶融ろう材５によって接合するに際して、前記
溶融ろう材５のうち余剰のろう材５ａは、他方の外部端
子３における端子片３ａに設けた切欠部７内の箇所に集
まり、当該箇所に、表面張力によって盛り上がることに
なるから、余剰の溶融ろう材５ａが、半導体チ・ノブ１
の外側面に向って大きく垂れ下がることを、確実に防止
できる。Then, when the terminal piece 3a of the other external terminal 3 is bonded to the upper surface of the P pole 1b of the semiconductor chip 1 with the molten brazing material 5 supplied therebetween, the excess brazing material of the molten brazing material 5 is removed. 5a gathers at a location within the notch 7 provided in the terminal piece 3a of the other external terminal 3, and swells at that location due to surface tension, so that the excess molten brazing material 5a is removed from the semiconductor tip 1.
It is possible to reliably prevent the material from hanging down significantly toward the outer surface of the material.

この場合において、他方の外部端子３における端子片３
ａに対して設ける切欠部としては、前記実施例のように
長溝状にする場合に限らず、第４図に示すように、端子
片３ａのの隅部に対して設けた切欠部７ａにしたり、或
いは、第５図に示すように、Ｖ型の切欠部７ｂに形成す
る等、他の形状にしても良いのである。In this case, the terminal piece 3 of the other external terminal 3
The notch provided for a is not limited to a long groove shape as in the above embodiment, but may be a notch 7a provided at the corner of the terminal piece 3a as shown in FIG. Alternatively, as shown in FIG. 5, other shapes may be used, such as a V-shaped notch 7b.

次に、第６図及び第７図は、前記請求項２に対する第１
の実施例を示すものであり、この実施例は、半導体チッ
プ１におけるＰ極１ｂの上面に、前記他方の外部端子３
における端子片３ａを、半田等のろう材５によって接合
するに際して、前記他方の外部端子３における端子片３
ａに、円形の抜き孔８を設けた構成にする。Next, FIGS. 6 and 7 illustrate the first aspect of claim 2.
This embodiment shows the other external terminal 3 on the upper surface of the P pole 1b of the semiconductor chip 1.
When joining the terminal pieces 3a in the other external terminal 3 with the brazing material 5 such as solder, the terminal pieces 3a in the other external terminal 3
A is provided with a circular punch hole 8.

このように、他方の外部端子３における端子片３ａに抜
き孔８を設けると、熔融ろう材５のうち余剰のろう材５
ａは、前記抜き孔８内に集まり、当該抜き孔８内に盛り
上がることになるから、余剰の熔融ろう材５ａが、半導
体チップ１の外側面に向って大きく垂れ下がることを、
確実に防止できる。In this way, when the punch hole 8 is provided in the terminal piece 3a of the other external terminal 3, the excess brazing material 5 of the molten brazing material 5 is removed.
a gathers in the punching hole 8 and rises inside the punching hole 8, so that the surplus molten brazing material 5a hangs down greatly toward the outer surface of the semiconductor chip 1.
It can definitely be prevented.

この場合において、他方の外部端子３における端子片３
ａに対して設ける抜き孔としては、前記実施例のように
円形にする場合に限らず、第８図に示すように矩形の抜
き孔８ａ、第９図に示すように楕円形の抜き孔８ｂ又は
第１０図に示すように十字形の抜き孔８Ｃ等、適宜形状
の抜き孔に形成しても良く、また、第１１図に示すよう
に複数個の抜き孔８ｄに構成しても良いのである。In this case, the terminal piece 3 of the other external terminal 3
The punch hole provided for a is not limited to a circular punch hole as in the above embodiment, but may also be a rectangular punch hole 8a as shown in FIG. 8, or an elliptical punch hole 8b as shown in FIG. Alternatively, as shown in FIG. 10, the hole may be formed in an appropriate shape, such as a cross-shaped hole 8C, or as shown in FIG. 11, it may be formed into a plurality of holes 8d. be.

更に、第１２図及び第１３図は、前記請求項３に対する
第１の実施例を示すものであり、この実施例は、半導体
チップ１におけるＰ極１ｂの上面に、前記他方の外部端
子３における端子片３ａを、半田等のろう材５によって
接合するに際して、前記他方の外部端子３における端子
片３ａの長さ寸法Ｓ２を、半導体チップ１におけるＰ極
１ｂの上面の一部が露出するように短くする構成にする
。Furthermore, FIGS. 12 and 13 show a first embodiment of claim 3, and in this embodiment, the other external terminal 3 is connected to the upper surface of the P pole 1b of the semiconductor chip 1. When joining the terminal pieces 3a with a brazing material 5 such as solder, the length dimension S2 of the terminal piece 3a in the other external terminal 3 is adjusted so that a part of the upper surface of the P pole 1b on the semiconductor chip 1 is exposed. Make it shorter.

このように、他方の外部端子３における端子片３ａの長
さ寸法Ｓ２を短くすることによって、半導体チップ１に
おけるＰ極１ｂの上面の一部が露出するようにすると、
溶融ろう材５の余剰のろう材５ａは、半導体チップ１に
おけるＰ極１ｂの上面のうち端子片３ａより露出する部
分に集まり、当該部分に、表面張力によって盛り上がる
ことになるから、余剰の溶融ろう材５ａが、半導体チッ
プ１の外側面に向って大きく垂れ下がることを、確実に
防止できる。In this way, by shortening the length dimension S2 of the terminal piece 3a in the other external terminal 3, a part of the upper surface of the P pole 1b in the semiconductor chip 1 is exposed.
Excess brazing filler metal 5a of molten brazing filler metal 5 gathers on the part of the upper surface of P pole 1b of semiconductor chip 1 that is exposed from terminal piece 3a, and bulges in that part due to surface tension. It is possible to reliably prevent the material 5a from hanging down greatly toward the outer surface of the semiconductor chip 1.

この場合において、半導体チップ１におけるＰ極１ｂの
上面の一部を、端子片３ａより露出するに際しては、前
記実施例のように、端子片３ａにおける長さ寸法Ｌ２を
短くすることに代えて、第１４図に示すように、端子片
３ａにおける幅寸法Ｓ２を狭くしたり、或いは、第１５
図に示すように、端子片３ａにおける長さ寸法Ｌ２を短
くすると共に、端子片３ａにおける幅寸法Ｓ２を狭くす
るように構成しても良いのである。In this case, when exposing a part of the upper surface of the P pole 1b of the semiconductor chip 1 from the terminal piece 3a, instead of shortening the length L2 of the terminal piece 3a as in the above embodiment, As shown in FIG. 14, the width dimension S2 of the terminal piece 3a may be narrowed, or
As shown in the figure, the length L2 of the terminal piece 3a may be shortened and the width S2 of the terminal piece 3a may be narrowed.

なお、これら第１２図〜第１５図に示す実施例において
、端子片３ａにおける長さ寸法Ｌ２を短くした場合には
、当該端子片３ａにおける先端面３　ｄｒに、第１６図
に示すように切欠部９を設けたり、又は、端子片３ａに
おける先端面３ａ′を、第１７図に示すように波型状に
構成することにより、また、端子片３ａにおける幅寸法
Ｓ２を狭くした場合には、当該端子片３ａにおける側端
面３ａ“に、第１８図に示すように切欠部ｌＯを設けた
り、又は、端子片３ａにおける側端面３ａ“を、第１９
図に示すように波型状に構成することにより、端子片３
ａに対するろう材５の接合面積の増大、延いては、端子
片３ａの半導体チップ１に対する接合力の増大を図るこ
とができる。In addition, in the embodiments shown in FIGS. 12 to 15, when the length dimension L2 of the terminal piece 3a is shortened, a notch is formed on the distal end surface 3 dr of the terminal piece 3a as shown in FIG. When the width dimension S2 of the terminal piece 3a is narrowed by providing the portion 9, or by configuring the tip end face 3a' of the terminal piece 3a in a wavy shape as shown in FIG. The side end surface 3a" of the terminal piece 3a is provided with a notch lO as shown in FIG. 18, or the side end surface 3a" of the terminal piece 3a is
By configuring the terminal piece 3 in a wave shape as shown in the figure,
It is possible to increase the bonding area of the brazing filler metal 5 to a, and by extension, increase the bonding force of the terminal piece 3a to the semiconductor chip 1.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図〜第３図は請求項１に対する実施例を示し、第１
図は縦断正面図、第２図は第１図の底面図、第３図は第
１図の平面図、第４図及び第５図は請求項１に対する他
の実施例を示す平面図、第６図は請求項２に対する実施
例を示す縦断正面図、第７図は第６図の平面図、第８図
、第９図、第１０図及び第１１図は請求項２に対する他
の実施例を示す平面図、第１２図は請求項３に対する実
施例をを示す縦断正面図、第１３図は第１２図の平面図
、第１４図、第１５図、第１６図、第１７図。 第１８図及び第１９図は請求項３に対する他の実施例を
示す平面図、第２０図は従来のダイオードの縦断正面図
、第２１図は第２０図の底面図、第２２図は第２０図の
平面図である。 ｌ・・・・半導体チップ、１ａ・・・・半導体チップに
おけるＮ極、１ｂ・・・・半導体チップにおけるＰＧＭ
、２・・・・一方の外部端子、２ａ・・・・一方の外部
端子における端子片、３・・・・他方の外部端子、３ａ
・・・・他方の外部端子における端子片、４，５・・・
・ろう材、６・・・・モールド部、７．７ａ、７ｂ・・
・・切欠部、８．８ａ、８ｂ、８ｃ、８ｄ−・−抜き孔
、Ｌ２・・・・他方の外部端子における端子片の長さ寸
法、Ｓ２・・・・他方の外部端子における端子片の幅寸
法。1 to 3 show embodiments of claim 1,
2 is a bottom view of FIG. 1, FIG. 3 is a plan view of FIG. 1, and FIGS. 4 and 5 are plan views showing other embodiments of claim 1. 6 is a longitudinal sectional front view showing an embodiment of claim 2, FIG. 7 is a plan view of FIG. 6, and FIGS. 8, 9, 10, and 11 are other embodiments of claim 2. FIG. 12 is a vertical sectional front view showing an embodiment of claim 3, FIG. 13 is a plan view of FIG. 12, FIG. 14, FIG. 15, FIG. 16, and FIG. 17. 18 and 19 are plan views showing other embodiments of claim 3, FIG. 20 is a longitudinal sectional front view of a conventional diode, FIG. 21 is a bottom view of FIG. 20, and FIG. FIG. l...Semiconductor chip, 1a...N pole in the semiconductor chip, 1b...PGM in the semiconductor chip
, 2... One external terminal, 2a... Terminal piece of one external terminal, 3... Other external terminal, 3a
...Terminal piece of the other external terminal, 4, 5...
・Brazing metal, 6...Mold part, 7.7a, 7b...
...Notch, 8.8a, 8b, 8c, 8d--Extraction hole, L2... Length dimension of the terminal piece in the other external terminal, S2... Length dimension of the terminal piece in the other external terminal Width dimension.

Claims (3)

【特許請求の範囲】[Claims] （１）、半導体チップを、金属板で形成された二枚の外
部端子における端子片の間に挿入し、該半導体チップに
おける一方の極の下面に、一方の外部端子における端子
片を、半導体チップにおける他方の極の上面に、他方の
外部端子における端子片を、各々ろう材にて接合して成
る半導体装置において、前記他方の外部端子における端
子片に、半導体チップの他方の極における上面のうち一
部の上面を露出するようにした切欠部を設けたことを特
徴とする半導体装置。(1) A semiconductor chip is inserted between the terminal pieces of two external terminals formed of metal plates, and the terminal piece of one external terminal is placed on the lower surface of one pole of the semiconductor chip. In a semiconductor device in which a terminal piece of the other external terminal is bonded to the upper surface of the other pole of the semiconductor chip using a brazing material, the terminal piece of the other external terminal is bonded to the upper surface of the other pole of the semiconductor chip. A semiconductor device characterized by having a cutout portion that exposes a portion of its upper surface. （２）、半導体チップを、金属板で形成された二枚の外
部端子における端子片の間に挿入し、該半導体チップに
おける一方の極の下面に、一方の外部端子における端子
片を、半導体チップにおける他方の極の上面に、他方の
外部端子における端子片を、各々ろう材にて接合して成
る半導体装置において、前記他方の外部端子における端
子片に、半導体チップの他方の極における上面のうち一
部の上面を露出するようにした抜き孔を設けたことを特
徴とする半導体装置。(2) Insert a semiconductor chip between the terminal pieces of two external terminals formed of metal plates, and place the terminal piece of one external terminal on the lower surface of one pole of the semiconductor chip. In a semiconductor device in which a terminal piece of the other external terminal is bonded to the upper surface of the other pole of the semiconductor chip using a brazing material, the terminal piece of the other external terminal is bonded to the upper surface of the other pole of the semiconductor chip. A semiconductor device characterized by having a punch hole that exposes a portion of its upper surface. （３）、半導体チップを、金属板で形成された二枚の外
部端子における端子片の間に挿入し、該半導体チップに
おける一方の極の下面に、一方の外部端子における端子
片を、半導体チップにおける他方の極の上面に、他方の
外部端子における端子片を、各々ろう材にて接合して成
る半導体装置において、前記他方の外部端子における端
子片の幅寸法及び長さ寸法のうちいずれか一方又は両方
を、半導体チップの他方の極における上面の一部が露出
するように短く又は狭くしたことを特徴とする半導体装
置。(3) Insert a semiconductor chip between the terminal pieces of two external terminals formed of metal plates, and place the terminal piece of one external terminal on the lower surface of one pole of the semiconductor chip. In a semiconductor device in which a terminal piece of the other external terminal is bonded to the upper surface of the other pole of the other external terminal using a brazing material, either one of the width dimension and the length dimension of the terminal piece of the other external terminal. or both of the semiconductor chips are shortened or narrowed so that a part of the upper surface of the other pole of the semiconductor chip is exposed.
JP63306336A 1988-12-02 1988-12-02 Semiconductor device Expired - Fee Related JP2510708B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63306336A JP2510708B2 (en) 1988-12-02 1988-12-02 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63306336A JP2510708B2 (en) 1988-12-02 1988-12-02 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH02152243A true JPH02152243A (en) 1990-06-12
JP2510708B2 JP2510708B2 (en) 1996-06-26

Family

ID=17955878

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63306336A Expired - Fee Related JP2510708B2 (en) 1988-12-02 1988-12-02 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2510708B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0936288A (en) * 1995-07-18 1997-02-07 Nec Corp Manufacture of semiconductor device
JP2012235161A (en) * 2012-08-01 2012-11-29 Rohm Co Ltd Structure of package type two-terminal semiconductor device
JP2016167480A (en) * 2015-03-09 2016-09-15 三菱電機株式会社 Power semiconductor device

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5116226U (en) * 1974-07-24 1976-02-05
JPS5130467U (en) * 1974-08-28 1976-03-05
JPS5678386U (en) * 1979-11-13 1981-06-25
JPS5727167A (en) * 1980-07-23 1982-02-13 Chuo Hatsumei Kenkyusho:Kk Painting equipment which has stable discharging amount of slurry
JPS58187156U (en) * 1982-06-08 1983-12-12 日本電気株式会社 integrated circuit container
JPS5939055A (en) * 1982-08-26 1984-03-03 Sanken Electric Co Ltd Manufacture of semiconductor device
JPS59158336U (en) * 1983-04-11 1984-10-24 日本電気株式会社 semiconductor equipment
JPS6175553A (en) * 1984-09-21 1986-04-17 Hitachi Tobu Semiconductor Ltd Electronic part
JPS6159355U (en) * 1984-09-21 1986-04-21
JPS61102794A (en) * 1984-10-26 1986-05-21 三菱電機株式会社 Terminal unit
JPS61115343A (en) * 1984-11-09 1986-06-02 Mitsubishi Electric Corp Semiconductor integrated circuit
JPS61177472U (en) * 1985-04-24 1986-11-05
JPS6217176U (en) * 1985-07-12 1987-02-02

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5116226U (en) * 1974-07-24 1976-02-05
JPS5130467U (en) * 1974-08-28 1976-03-05
JPS5678386U (en) * 1979-11-13 1981-06-25
JPS5727167A (en) * 1980-07-23 1982-02-13 Chuo Hatsumei Kenkyusho:Kk Painting equipment which has stable discharging amount of slurry
JPS58187156U (en) * 1982-06-08 1983-12-12 日本電気株式会社 integrated circuit container
JPS5939055A (en) * 1982-08-26 1984-03-03 Sanken Electric Co Ltd Manufacture of semiconductor device
JPS59158336U (en) * 1983-04-11 1984-10-24 日本電気株式会社 semiconductor equipment
JPS6175553A (en) * 1984-09-21 1986-04-17 Hitachi Tobu Semiconductor Ltd Electronic part
JPS6159355U (en) * 1984-09-21 1986-04-21
JPS61102794A (en) * 1984-10-26 1986-05-21 三菱電機株式会社 Terminal unit
JPS61115343A (en) * 1984-11-09 1986-06-02 Mitsubishi Electric Corp Semiconductor integrated circuit
JPS61177472U (en) * 1985-04-24 1986-11-05
JPS6217176U (en) * 1985-07-12 1987-02-02

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0936288A (en) * 1995-07-18 1997-02-07 Nec Corp Manufacture of semiconductor device
JP2012235161A (en) * 2012-08-01 2012-11-29 Rohm Co Ltd Structure of package type two-terminal semiconductor device
JP2016167480A (en) * 2015-03-09 2016-09-15 三菱電機株式会社 Power semiconductor device

Also Published As

Publication number Publication date
JP2510708B2 (en) 1996-06-26

Similar Documents

Publication Publication Date Title
JP2875139B2 (en) Method for manufacturing semiconductor device
US6501160B1 (en) Semiconductor device and a method of manufacturing the same and a mount structure
JP2000208690A (en) Lead frame, resin-encapsulated semiconductor device and method of manufacturing the same
JP2857648B2 (en) Electronic component manufacturing method
JPH03222464A (en) Semiconductor device and its manufacture
KR100237912B1 (en) Packaged semiconductor, semiconductor device using same, and method for manufacturing same
JP2510708B2 (en) Semiconductor device
JPS6097654A (en) Sealed type semiconductor device
JP2647900B2 (en) Surface mount ultra-thin semiconductor device
JPS61279141A (en) Direct connection apparatus and method for lead frame with flexible tapered lead and mechanical die support
KR910000018B1 (en) Semiconductor device using the lead-frame and method of manufacture there of
JP2504187B2 (en) Lead frame
JPH09129796A (en) Semiconductor device
JPS63311732A (en) Method of packaging semiconductor element
JPS6175553A (en) Electronic part
JPS61237454A (en) Electronic part
KR100226773B1 (en) Package of Semiconductor Devices
JPS59110146A (en) Outer lead terminal of package type module
JPH04199739A (en) Lead frame for semiconductor device
KR940010298A (en) Semiconductor package and manufacturing method thereof
KR0157892B1 (en) Chip size semiconductor package and manufacturing method thereof
JPH03147355A (en) Manufacture of semiconductor device
JPS59231842A (en) Semiconductor device
JPH03149893A (en) Semiconductor device
KR930007927Y1 (en) Lead-frame

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees