JPH02152255A - How to form multilayer wiring - Google Patents

Abstract

PURPOSE:To control a final film thickness of an interlayer insulating film by a method wherein, after a lower-layer wiring part has been formed, a silicon nitride film is deposited or, after a metal film has been deposited, the silicon nitride film is deposited on it, the metal film and the silicon nitride film are patterned and the silicon nitride film is formed on the lower-layer wiring part. CONSTITUTION:An insulating film 12 is formed on a silicon substrate 11 where a semiconductor element has been formed; a first aluminum wiring part 13 is formed on it; a silicon nitride film 14 by a plasma CVD method is deposited on it at a thin film thickness; e.g. 50nm; in addition, a silicon oxide film 15 by the plasma CVD method is deposited; a resist 16 is coated. Then, the P-SiN 14 on the first aluminum wiring part 13 is etched back until it is exposed under a condition that an etching rate of the p-SiO2 is nearly equal to that of the resist 16. In order to detect this exposure of the p-SiN 14, e.g. emitted light of a plasma is separated into its spectral components and the emitted light of nitrogen at 674nm is monitored. The remaining resist 16 is removed; after that, a p-SiO2 17 is deposited as an interlayer insulating film; a through hole 18 is made; a second aluminum wiring part 19 is formed; a two-layer aluminum wiring part is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for forming multilayer wiring in a semiconductor integrated circuit.

2. Description of the Related Art A two-layer aluminum wiring process using a conventional method for forming multilayer wiring will be explained with reference to FIGS. 4(a) to 4(f). First, in FIG. 4(a), an insulating film 42 is formed on a silicon substrate 41 on which a semiconductor element is formed, and a first aluminum wiring 43 is formed thereon.

Next, a silicon oxide film 44 is deposited as an interlayer insulating film (see FIG. 4(b)).

If a second layer of aluminum wiring is formed in this state, disconnections or short circuits will occur in the second layer, so it is necessary to planarize the interlayer insulating film. Therefore, a resist 45 is applied (see FIG. 4 (2)), and etched just before or until the first aluminum wiring 43 is exposed under conditions such that the etching rates of the silicon oxide film 44 and the resist 45 are approximately equal. (see FIG. 4(d)). After removing the remaining resist 45, a silicon oxide film 46 is deposited as an interlayer insulating film (see FIG. 4(e)), a through hole 47 is opened, and a second An aluminum wiring 48 is formed to form a two-layer aluminum wiring (see FIG. 4(f)).

In the method described above, when the distance between the first layer aluminum wirings is relatively large, no gap is created in the interlayer insulation film as shown in FIG. 4(f), but as shown in FIG. As the spacing between layer aluminum wiring becomes smaller, the deposited silicon oxide film 44 becomes overhanging.
As shown in ~, gaps 49 are created between the aluminum wirings. At this time, as shown in Fig. 4(i), the aluminum wiring 4
Etch back until the top of 3 is completely exposed,
By depositing the silicon oxide film 46, it is possible to prevent gaps from forming as shown in FIG. 4U). An example of such a conventional technique is JP-A-58-197852.

Problems to be Solved by the Invention However, in the conventional method of forming multilayer wiring,
If the first layer of aluminum wiring is exposed during etchback of the resist and silicon oxide film, the aluminum wiring will be exposed to plasma during etchback and will be damaged by ion irradiation, resulting in disconnection and reliability problems. There was a problem in that the value decreased. This is particularly a serious problem when the aluminum wiring becomes fine and the upper part of the aluminum wiring is exposed as shown in FIG. 4(i). In addition, in order to avoid exposing the aluminum wiring, it is important to finish etching before the aluminum wiring is exposed.
It is necessary to accurately control the etching speed of the resist and silicon oxide film, but it is difficult to control all of this, resulting in poor controllability, which causes the film thickness left on the aluminum wiring to vary each time, resulting in Another problem was that it was difficult to control the thickness of the interlayer insulating film.

An object of the present invention is to prevent the above-mentioned problems and form fine multilayer wiring.

Means for Solving the Problems In the present invention, in order to solve the above-mentioned problems, a silicon nitride film is deposited after forming the lower layer wiring, or a silicon nitride film is deposited on the metal film that will become the lower layer wiring. The metal film and the silicon nitride film are patterned to form a silicon nitride film on the lower wiring. Furthermore, the etch-back after exposing the silicon nitride film on the lower wiring is continued under conditions such that the etching rate of the silicon oxide film is higher than the etching rate of the silicon nitride film.

Function: With the above-described configuration, the present invention monitors the etching status of the silicon nitride film after the silicon nitride film on the lower layer wiring is exposed, thereby determining the end of etchback and changes in etchback conditions. As a result, variations in film thickness on the lower layer wiring can be suppressed. Also,
By changing the etchback conditions after the silicon nitride film is exposed during etchback, the silicon nitride film is present on the lower wiring during etchback, so it is possible to prevent the lower wiring from being exposed to plasma. It is possible to prevent damage to the underlying wiring due to ion irradiation, prevent wire breakage, and improve the reliability of the wiring.

Embodiment FIGS. 1(a) to 1(e) show cross-sectional views of the process when applied to two-layer aluminum interconnection as a first embodiment of the multilayer interconnection forming method of the present invention. First, an insulating film 12 is formed on a silicon substrate 11 on which a semiconductor element is formed, and a first aluminum wiring 13 is formed thereon.
A silicon nitride film 14 (hereinafter a silicon nitride film produced by plasma CVD method will be abbreviated as p-3iN) by method D is deposited to a thin film thickness of, for example, 50 nm, and then further deposited by plasma CVD.
A silicon oxide film 15 (hereinafter, a silicon oxide film formed by plasma CVD method will be abbreviated as p-8i02) is deposited using the plasma CVD method, and a resist 16 is applied (see FIG. 1(a)). Next, under conditions where the etching speeds of the p-8iO
(See figure (b)). Detection of this p-3iN14 exposure is
For example, this can be done by spectroscopy of plasma emission and monitoring nitrogen emission at 674 nm. For example, the end point of etchback is the point where the emission intensity starts to rise or the point where the emission intensity is saturated. Good. Thereafter, after removing the remaining resist 16, p-3iO, 17 is deposited as an interlayer insulating film.
In the figure (see (2)), the through hole 18 is opened and the second aluminum wiring 19 is formed to form a two-layer aluminum wiring (
(See Figure 1 (cl)).

Note that in this embodiment, p-3i on the first aluminum wiring 13
Although the etch-back was terminated by exposing the N14, the etch-back may be terminated once the p-8iN14 on the aluminum wiring 13 is removed.In this case, the etch-back may be terminated at the point where the nitrogen emission intensity begins to decrease or becomes saturated after decreasing. That should be the ending point. Furthermore, although it is not necessary to finish this etchback after exposing or removing the p-8iN14, from the viewpoint of controlling the interlayer film thickness, it is necessary to finish the etchback after the exposure of the p-8iN1.
This is convenient because the sum of the deposited film thickness of p-3i○217 and the deposited film thickness of p-3i○217 becomes the deposited film thickness of p S t 0217 after removal. In addition, the etchback conditions at this time are such that the etchback rate of the silicon oxide film is 0.5% of that of the resist.
The appropriate etching rate for the silicon nitride film is 8 to 1.2 times, but the etching rate for the silicon nitride film can be set arbitrarily, but when the etch back is completed by exposing the silicon nitride film on the underlying wiring, it is relatively small and cannot be removed. When doing so, it is desirable to have a relatively large size.

In addition, if the flatness shown in Figure 1 ((2) causes a risk of disconnection or short circuit when forming the second aluminum wiring &1119, the film thickness of p-8f0217 should be set as the film thickness planned as the interlayer insulating film. Deposit thicker, apply resist, p
If the p-3iO217 is etched back to the desired film thickness under conditions where the etching rates of the -8iO217 and the resist are approximately equal, good flatness as shown in FIG. 1(e) can be obtained.

After that, the through hole 18 is opened and the second aluminum wiring 19 is inserted.
By forming this, a two-layer aluminum wiring without disconnections or short circuits can be obtained.

FIGS. 2(a) to 2(e) show process cross-sectional views of a second embodiment of the multilayer interconnection forming method of the present invention when applied to a two-layer aluminum interconnection. First, an insulating film 22 is formed on a silicon substrate 21 on which a semiconductor element is formed, and a first aluminum wiring 23 with a finer wiring width and smaller wiring spacing than in the first embodiment is formed thereon. , p-5iN24 is deposited, for example, to a thickness of 150 nm, and further p SiO225
is deposited, and a resist 26 is applied (see FIG. 2(a)). Next, under conditions where the etching rates of the pS 10225 and the resist 26 are approximately equal, etching is performed until the p-8iN 24 on the first aluminum wiring 23 is exposed (see FIG. 2(b)).

After this, the etching rate of pSio225 was p-8iN.
Etching back is performed in a range where the aluminum wiring 11123 is not exposed under the conditions that the etching rate is higher than that of 24 (see FIG. 2 (2)). Since this can be easily detected by the exposure of 3iN24, for example, the same method used to detect the exposure of p-3fN14 in the first embodiment may be used.Next, after removing the remaining resist 26, the p-3i0227 is deposited as an insulating film between the eyebrows (see FIG. 2(d)), and a through hole 28 is opened to form a second aluminum wiring 29 to form a two-layer aluminum wiring (second aluminum wiring).
(See figure (e)).

Note that in this example, after changing the etchback conditions, the etchback was completed within a range where the first aluminum wiring 23 was not exposed, but the etchback was completed when the p-8iN 24 on the aluminum wiring 23 was removed. Also good. This P-8
Detection of removal of iN24 is performed by p in the first embodiment.
A method similar to that used to detect the removal of -3iN14 may be used. The etch-back conditions before exposing the silicon nitride film on the lower wiring are the same as those described in the first embodiment, but it is desirable that the etching rate of the silicon nitride film is relatively low.

Etch-back conditions after exposing the silicon nitride film are as follows:
The etching rate of the silicon oxide film is preferably about 1.5 to 4 times the etching rate of the silicon nitride film, and the etching rate of the resist may be set at any rate. Also, the second
If forming the second aluminum wiring 29 with the flatness shown in FIG. All you have to do is apply it and etch back to increase the flatness.

In the first and second embodiments described above, p-3iN is deposited after aluminum wiring is formed, and p-3iN is deposited on the aluminum wiring.
Although 8iN is formed, it is also possible to take the steps shown below. That is, as shown in FIG. 3(a), an aluminum film 33 is continued to be deposited on a portion where an M832 is formed on a silicon substrate 31 on which a semiconductor element is formed.
3iN34 is deposited to form a resist 35 for a wiring pattern. Next, using this resist 35 as a mask, the aluminum film 33 and p-5iN 34 are dry etched.
When the resist 35 is removed, p-3iN 34 can be formed only on the aluminum wiring 36 as shown in FIG. 3(b), and after this, the first and second
A multilayer wiring can be formed in the same manner as in the embodiment.

In the examples described above, a silicon oxide film formed by plasma CVD was used as the silicon oxide film, but silicon oxide films formed by other methods, such as photoCVD or TE01 (tetraethlorth
A silicon oxide film using phosphorus or boron as an impurity may be used. Further, the silicon oxide film deposited the first time and the silicon oxide film deposited the second time may be of different types. Although a silicon nitride film made by plasma CVD is used, silicon nitride films made by photo-CVD or low-pressure CVD may also be used. Aluminum was used as the metal film forming the wiring, but aluminum alloys containing silicon, copper, etc. may also be used.
It may be a high melting point metal such as tungsten, a silicide such as tungsten silicide or titanium silicide, polycrystalline silicon, or a laminated film of these.

Further, instead of the resist used when etching back the silicon oxide film and the resist, an organic resin film, such as a polyimide film, which is formed flat by spin coating may be used.

Effects of the Invention As described above, according to the present invention, by monitoring the etching status of the silicon nitride film on the lower layer interconnection using emission spectroscopy after the silicon nitride film is exposed, it is possible to check whether the etchback is complete or not. Since changes in back conditions can be seen, controllability is improved and variations in film thickness on lower layer wiring can be suppressed. In addition, by changing the etch-back conditions after the silicon nitride film is exposed during etch-back,
Since the silicon nitride film is present on the lower layer wiring during etchback, it can prevent the lower layer wiring from being exposed to plasma, and the lower layer wiring will not be damaged by ion irradiation (preventing wire breakage). In addition, the reliability of wiring can be improved. In particular, the method of the second embodiment allows formation of fairly fine multilayer wiring with good wiring reliability without creating gaps between wirings.

[Brief explanation of the drawing]

FIG. 1 is a process sectional view showing the first embodiment of the present invention, FIG. 2 is a process sectional view showing the second embodiment of the invention, and FIG.
The figure is a cross-sectional view of the process for forming p-8iN on aluminum wiring, and FIG. 4 is a cross-sectional view of the process of the prior art. 13.23...First aluminum wiring, 14.24.
...p-3iN, 15.17, 25.27...
...p-8i02.16.26...Resist. Name of agent: Patent attorney Shigetaka Awano and 1 other prefectural maps

Claims (5)

[Claims] (1) Depositing a silicon oxide film on a substrate on which a silicon nitride film has been deposited after forming a lower wiring layer, then applying a resist, and etching back the silicon oxide film and the resist at approximately the same speed; After the silicon nitride film on the lower wiring is exposed, etchback is completed, the resist is removed, a silicon oxide film is deposited, and a through hole is formed in the silicon oxide film and silicon nitride film on the lower wiring. 1. A method for forming multilayer wiring, comprising forming an opening and forming an upper layer wiring. (2) On the substrate on which the silicon nitride film has been deposited after forming the lower wiring layer, a silicon oxide film is deposited, a resist is applied, and the silicon oxide film and the resist are etched at approximately the same speed. After the silicon nitride film on the lower wiring is exposed, etch back is performed under conditions such that the etching rate of the silicon oxide film is higher than the etching rate of the silicon nitride film to the extent that the silicon nitride film on the lower wiring is not removed. After removing the resist and depositing a silicon oxide film, a through hole is opened in the silicon oxide film and silicon nitride film on the lower layer wiring to form an upper layer wiring. How to form. (3) The method for forming a multilayer wiring according to claim 2, wherein the etch-back after the silicon nitride film is exposed is completed when the silicon nitride film on the lower wiring is removed. (4) Instead of using a substrate on which a silicon nitride film is deposited after forming a lower wiring layer, depositing a metal film forming a lower wiring layer, depositing a silicon nitride film, and patterning the metal film and silicon nitride film, Claims 1 to 3 characterized in that a substrate is used in which a silicon nitride film is formed only on the lower layer wiring.
The method for forming a multilayer wiring according to any one of the above. (5) The multilayer wiring according to any one of claims 1 to 4, characterized in that a polyimide film is applied and used in place of a resist when etching back a silicon oxide film formed on a silicon nitride film. Formation method.