JPH0215657A - Wiring structure and wiring method for repairing semiconductor integrated circuits - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to the repair of integrated circuits in which the logic of semiconductor integrated circuits is changed by cutting, wiring, etc. on the chip after the chip is manufactured. The present invention relates to a repair wiring structure and a repair wiring method for semiconductor integrated circuits for facilitating processing and improving the yield of repaired integrated circuits. ■Prior art] In recent years, as semiconductor integrated circuits (hereinafter referred to as LSIs) have become highly integrated and miniaturized, it has become necessary to cut some of the wiring within the LSI chip or create new wiring during the development process. There have been reports of cases in which the defective parts are corrected and the logic of the LSI is changed in a short period of time. As such a conventional technique, for example, Japanese Patent Application Laid-Open No. 52-2
No. 29956 describes a method of making holes and cutting wires using a laser or a focused ion beam, and forming connection wires using a CVD method. Furthermore, Japanese Patent Application Laid-Open No. 62-298134 discloses a technique for making connections between wirings easier during repairs by providing a spare wiring inside an LSI and using this spare wiring when changing the logic. There is. [Invention or section to be solved WU1 By the way, as shown in FIG.
L1. For example, as shown in the same figure (a), the top layer A has a multilayer structure consisting of AL2 and Al1.
Since the wiring patterns 66 and 64 belonging to L3 are close to each other, when the wiring pattern 66 is cut, there is a risk that part of the adjacent wiring pattern 64 will also be cut. In addition, as shown in FIG. 3(b), the wiring pattern layer AL2
When cutting the wiring pattern 69 at its part 62, because the wiring patterns 63 and 61 belonging to the upper wiring pattern layer AL3 are close to each other, one of them, for example, a part of the wiring pattern 61 or There is a risk that the whole thing will be cut off. As described above, the existence of the possibility of cutting a wiring pattern other than the intended wiring pattern reduces the reliability of the repaired LSI. In addition, when forming a new wiring pattern for repair, as shown in FIG. 3(C), part of the surface of the wiring pattern 72 to which the new wiring pattern 70 is to be connected is need to be exposed. that time,
There is a possibility that a portion of adjacent wiring patterns 71 may be exposed at the same time, and in that case, when wiring pattern 70 is formed, wiring patterns 71 and 72 will be short-circuited. Similarly, as shown in FIG. 3(d), a new wiring pattern 60 is added to the wiring pattern 69 of the lower layer AL2.
When exposing a portion of the wiring pattern 69 to connect the wiring pattern 68, there is a risk that a portion of the upper layer wiring pattern 68 may be cut. In this case as well, when the wiring pattern 60 is formed, a situation may arise in which the wiring patterns 68 and 69 are short-circuited. Such short circuits have been repaired and sr.
may cause malfunction. When cutting and connecting miniaturized wiring patterns, a high level of processing precision is required to prevent undesirable situations such as cutting of unintended wiring patterns and short circuits as described above. Requires expensive repair equipment such as high-precision ion beam equipment. Moreover, even with such highly accurate equipment, it is difficult to process multilayer wiring and fine, highly integrated wiring, and the yield of processed LSIs also decreases. . An object of the present invention is to provide a repair wiring structure and a repair wiring method for semiconductor integrated circuits that can improve the yield of repaired LSIs. Another object of the present invention is to provide a wiring structure for repairing a semiconductor integrated circuit and a wiring method for repairing, which can alleviate requirements for alignment accuracy, processing accuracy, etc. of a repair device. 1 Means for Solving the Problems 1 The wiring structure for repairing a semiconductor integrated circuit according to the present invention includes, for a specific wiring pattern, a part of the wiring pattern adjacent to the specific wiring pattern, which includes both of the wiring patterns. This feature is characterized by the provision of a detour portion that expands the interval. The detour portion of the adjacent wiring pattern is provided in the same layer as the adjacent wiring pattern, or the detour portion of the adjacent wiring pattern is provided in a layer different from the adjacent wiring pattern via a through hole. be able to. When provided in different layers, it is preferable to provide the layer above the layer of the adjacent wiring pattern. According to another aspect of the wiring structure for repairing a semiconductor integrated circuit according to the present invention, for two substantially parallel adjacent wiring patterns, a part of both wiring patterns is repaired by expanding the interval between the two wiring patterns. The present invention is characterized in that a repair area is provided, and the repair area is used for repair by changing the wiring after the chip is manufactured. Further, the wiring method for repairing a semiconductor integrated circuit according to the present invention is a wiring method for repairing a semiconductor integrated circuit to create a wiring pattern for repairing a semiconductor integrated circuit after manufacturing a chip. First, focus on the vine wiring pattern that is the target of repair, and check whether there is a gap between the wiring pattern and the wiring pattern adjacent to the wiring pattern, or if there is a part that is wider than the predetermined interval. , if the result of the check is negative, a detour section is provided that increases the distance from the noted wiring pattern by the predetermined distance by changing the route of the adjacent wiring pattern. That is. More specifically, the repair wiring method for a semiconductor integrated circuit according to the present invention is a repair wiring method for creating a wiring pattern for repairing one semiconductor integrated circuit after chip manufacturing, comprising:
a) Perform wiring without considering the spacing between adjacent wiring patterns,
b) Register wiring patterns that may be subject to repair; C)
For each of the registered wiring patterns, search for a wiring pattern adjacent to the wiring pattern, and d) for one of the registered wiring patterns, if there is a part with a gap between the adjacent wiring pattern or a part wider than a predetermined gap. e) If the result of the check is positive, register the area as a repair area; and f) If the result of the check is negative, take appropriate measures. g) by changing the route of the adjacent wiring pattern at the location, providing a detour part that makes the interval with the focused wiring pattern larger than the predetermined interval, and registering the location as a repair area; g) This method is characterized in that steps C) to f) are repeated for all the registered wiring patterns. The check in step d) is performed, for example, on one of the registered wiring patterns, sequentially for each location for each unit length, from one end of the wiring pattern to the other end. After steps C) and f) and/or after step g), the registration result of the repair area may be output to an output device. For example, it is possible to display a list on a display device, a printer, etc., or to display a graphic on a graphic display device, an X-Y plotter, etc. The adjacent wiring patterns to be checked are as follows:
Not only the wiring pattern in the same layer as the noted wiring pattern, but also the wiring pattern in the L layer from that layer.
The wiring pattern of the upper layer can be taken into consideration by applying it to the layer. Preferably, the detour portion is provided in the same layer as the adjacent wiring pattern or in an upper layer. Note that in this specification, "wiring" does not refer to the act of forming conductive wires in the actual LSI, but rather to
This refers to determining the arrangement of wiring patterns within I. 1 Effect 1 The present invention proactively provides a repair area in advance in each part of an LSI that may need or may require repair after LSI manufacture, and within this repair area, there is a gap between adjacent wiring patterns. Provide areas that are enlarged beyond a certain interval. At the time of repair, existing wiring is cut and new wiring is formed within one of these repair areas. In other words, when cutting existing wiring, the area within the repair area of the target wiring pattern is set at a spacing between adjacent wiring patterns or a predetermined spacing.
If the cutting is performed within the repair area, there is no possibility that the adjacent wiring pattern will be cut due to insufficient processing precision. In addition, when forming a new wiring pattern, if the wiring pattern is formed within the repair area of the target wiring pattern, short circuits to adjacent patterns may occur due to insufficient positioning and processing accuracy. It also disappears. Preferably, if repair areas are provided between all terminals, between terminals and branch points, and between branch points, any logic change can be coped with. In addition,
A branch point is a point where three or more wiring patterns are derived from a - point. Thus, according to the invention, iI! Highly reliable repairs can be performed without requiring S degree alignment and processing accuracy. Therefore, the yield of repair and SI can be improved without using ultra-high precision repair equipment. Of course, the present invention does not prohibit the use of ultra-high-precision repair equipment, and if such equipment is used, it will be even easier to repair detailed and complex multilayer wiring patterns. It is easy to understand what will happen. The method for cutting and forming the wiring pattern is as follows:
Said Japanese Unexamined Patent Publication No. 12-229956, 62-2981
A known method such as that disclosed in No. 14 can be used. [Example 1] Hereinafter, regarding an example of the present invention using a logic LSI as an example,
This will be explained in detail with reference to the drawings. FIG. 1 shows a schematic configuration of a part of one wiring layer inside an LSI having multilayer wiring. Within the LSI, there are areas (called cells) A-, -F in units of logic circuits such as logic gates.
Each cell has one terminal for connection to other cells, etc.
~7 are provided. In this example, the state before repair is cell A. B and C are in a logical connection relationship, and their respective terminals 1 to 3 are connected to each other. That is, the terminal l is sequentially connected to the wiring pattern 31 . Through hole 11, wiring pattern 32
．． The terminal 2 is connected to the terminal 2 via the through hole 12 and the wiring pattern 33, and the terminal 2 is connected to the wiring pattern 33, the through hole 12, the wiring pattern 34, and the through hole 13 in this order.
, are connected to the terminal 3 via the wiring pattern 35. On the other hand, cells D, E, and F are also in a logical connection relationship, and are connected to the respective terminals 4 to 6 or phase. That is, the terminal 4 is connected to the wiring pattern 36 at 111'
, through hole 14, wiring pattern 37, through hole 15, and wiring pattern 39, terminal 5 is connected to wiring pattern 39 through hole 15 in order.
, wiring pattern 40, through hole 16, wiring pattern 41, through hole 17, wiring pattern 42. Through hole 18, wiring pattern 43, through hole 19, wiring pattern 44, through hole 20, and wiring pattern 4
5 to terminal 6. In this embodiment, a repair area 101 is provided between through holes 11.12 and 14.15, and a repair area 101 is provided between through holes 12.13 and 15.20.
A repair area 102 is provided in between. In this case, through hole 12 and through hole 15 constitute a branch point of the wiring pattern. If possible, use terminal 2 and through hole 1 as a repair area between the terminal and the branch point.
It is preferable to provide a repair area between the terminal 5 and the through hole 15 as well as between the terminal 5 and the through hole 15. In the repair area 101, a curved part or detour part 38 is provided in a part of the wiring pattern 37 between the through-holes 14 and 15, which deviates from the straight line connecting both through-holes in the same layer, so that the adjacent wiring pattern 32 Extending the interval between. This expansion width is set to a width that does not interfere with adjacent wiring patterns during processing associated with repair such as cutting and forming wiring patterns. This width also varies depending on the processing accuracy of the repair equipment used. In the repair area 102, a detour portion 46 is provided in the wiring pattern between the through holes 15 and 20. However, the wiring patterns 41 to 43 that constitute this detour portion 46
Unlike the detour portion 38, the through holes 16 to 19 are provided in other wiring pattern layers. The wiring patterns 41 to 43 do not necessarily need to be provided in the same layer, and it is desirable that at least the wiring pattern 42 be provided in a layer above the layer shown in FIG. As shown in Figure 3,
Generally, the even-numbered layers and odd-a-th layers of wiring pattern layers cross in the direction in which the wiring patterns run, and the gaps (channels) between the wiring patterns that can be used for new wiring also cross. I often find myself running in the same direction. I wanted to-
For example, if the layer shown in FIG. 1 is the Al1 layer,
It is conceivable that the wiring patterns 41 and 43 are provided on the Al1 layer, and the wiring pattern 42 is provided on the Al1 layer. If the wiring pattern of the detour part is provided on the same layer as in repair area +01, the number of through holes can be reduced. On the other hand, if the wiring pattern of the detour part is provided on the upper layer like the repair area 102, the number of through holes will increase, but if, for example, it becomes necessary to repair the wiring pattern between terminals 5 and 6, There is an advantage of being able to process the upper layer. If the wiring pattern 46 is provided on the uppermost layer, there is no need to consider the wiring pattern in the upper layer when cutting the wiring pattern, and since it can be processed with a shallow hole, processing becomes easy and processing defects can be reduced. Now, in FIG. 1, suppose that it is necessary to change the logic by reconnecting terminal 2 of cell B to terminal 7 of cell F instead of terminal 3 of cell C. In this case, first, the wiring pattern 34 is removed by a conventional method using a laser or a focused ion beam, etc. in the X" portion of the repair area 102.
cut. At this time, as shown in Figure 1, since there is sufficient space between adjacent wiring patterns, the wiring pattern that has just been cut is A wiring 50 is applied from a point on the terminal 2 side of 34 to the terminal 7. This wiring 50 is shown as being connected by a discrete wire, but this is only shown schematically. . FIG. 2 shows an LSI structure of the present invention in contrast to the conventional case shown in FIG. FIG. 2 shows an LSI according to the present invention.
FIG. 3 is a cross-sectional view of a repair area. In FIG. 2(a), as can be seen from a comparison with FIG. 3(a), the spacing between the adjacent wiring patterns 64 and 66 of the Al1 layer has been expanded, so that the wiring can be easily processed without requiring high processing accuracy. Only pattern 66 can be cut correctly. Similarly, in the case of FIG. 2(b), since the wiring pattern 61 is separated from the adjacent wiring pattern 63 by a predetermined distance or more, when cutting the lower layer wiring pattern 62, even with normal processing accuracy, the "- layer" Neither the wiring patterns 61 nor 63 will be damaged. In addition, in the case of FIG. 2(c), compared to the case of FIG. 3(c), since the wiring pattern 71 or the wiring pattern 72 is separated by a predetermined distance or more, the adjacent wiring pattern 7172 in the same layer is The wiring pattern 70 reduces the risk of short circuit. Similarly, in the case of FIG. 2(d), the wiring pattern 68 is separated from the wiring pattern 67 compared to the case of FIG.
The possibility of short-circuiting of wiring patterns between upper and lower layers is reduced through this method. Next, an example of the repair area creation process as shown in FIG. 1 will be described with reference to the flowchart in FIG. 4. First, conventional general automatic wiring is performed without considering the repair area (SO). Therefore, all wiring patterns that can be repaired are registered (Sl). The unit of this wiring pattern is a wiring pattern between one terminal and, if there is a branch, a wiring pattern between a terminal and a branch point or between a branch point and a branch point. As the wiring pattern to be registered, for example, a specific wiring group whose logic is frequently changed, such as a clock signal pattern, may be specified. Alternatively, the process may be performed only on wiring patterns within a certain range. This eliminates wiring pattern changes that rarely involve logic changes, and speeds up the process of the present invention and improves wiring efficiency and wiring density. I can plan something. Next, for each wiring pattern registered in this way, adjacent wiring patterns are searched and recognized (S2). In this case, as for the "adjacent wiring pattern", it is necessary to consider not only the wiring pattern in the same layer as the wiring pattern but also the wiring pattern in the upper layer. Because the repair
This is because, as mentioned above, it is performed from the surface of the LSI. Therefore, when considering whether a wiring pattern in a certain layer is adjacent to a wiring pattern in another layer, it is only necessary to consider the layers above that layer. The wiring pattern of ALI or the layer above it, for example, Al
By mapping the wiring pattern of the first layer AL3 onto the layer ALI, it can be determined whether the wiring pattern is adjacent to the first wiring pattern as a relationship within the same layer. Furthermore, among the wiring patterns in the upper layer, wiring patterns that intersect with the wiring pattern of interest are also considered as "adjacent wiring patterns." Next, it is checked whether or not there is a predetermined distance between all the wiring patterns determined to be adjacent to each other at any part of a certain wiring pattern (S3).
For example, the distance between adjacent wiring patterns is inspected by shifting the inspection location by a unit length from one end of the wiring pattern to the other end. In this case, as described above, the adjacent wiring pattern also includes the upper layer wiring pattern. If there is a location that satisfies the conditions of Stellaf S3, that area is registered as a repairable area, that is, a repair area (S5). If there are no locations where the above conditions are met, at least - new repair areas are provided (S4);
It is preferable to select a position where there is no need to change the intersecting wiring patterns on the upper layer.
That is, the detour portion is formed by changing a part of the parallel adjacent wiring pattern routes. As shown in Figure 1, there are at least two types of the repair area (
Repair areas 101 and 102) are considered. At this time, changes to the net in areas that have already been registered as repair areas are prohibited. The new repair area created in this way is also registered (S5). This process is repeated for all wiring patterns (Sa), and when completed, an appropriate output device (not shown) is
For example, the wiring pattern is displayed for each layer on a graphic display device or an x-y plotter, and the registered repair area is also displayed on the wiring pattern. (S7) The output mode of the registration result of the repair area is not limited to such a graphic display, but may be displayed as a list using characters, symbols, etc., as long as the result can be recognized by the operator. This allows you to confirm the location of the registered repair area. Furthermore, this display helps in determining which part of the wiring pattern should be cut and which part should be wired when repair is required. The process shown in FIG. 4 can be performed manually or preferably automatically by a computer program. In this computer program, each wiring pattern is defined as a connection of coordinate points, and processes such as calculating the distance between adjacent patterns and changing the wiring pattern route are performed by calculating coordinate values,
This can be done by making changes, etc. Although only preferred embodiments of the present invention have been described above, those skilled in the art will readily understand that various changes and modifications can be made without departing from the gist of the present invention. Effects of the Invention 1 According to the present invention, for example, by providing a repair area in advance as a dedicated place for cutting and connecting wiring patterns when changing logic after LSI change, processing during LSI repair can be improved. Since the requirement for accuracy is relaxed, processing becomes easier and processing defects are reduced, resulting in an increase in the success rate of logic changes and an improvement in the yield of repaired LSIs.

[Brief explanation of the drawing]

Fig. 1 is a schematic diagram of the inside of an LSI to which the present invention is applied, Fig. 2 is a sectional view of a repaired LSI according to the present invention, Fig. 3 is a sectional view of a conventional repaired LSI, and Fig. 4 is a sectional view of the repaired LSI of the present invention. 3 is a flowchart of one embodiment of a wiring method. 1 to 7...terminals, 11 to 20...through holes. 31-45...Wiring pattern, A-F...Cell, 1
01, 102...Repair area diagram 2

Claims (1)

[Claims] 1. A detour section is provided in a part of the wiring pattern adjacent to the specific wiring pattern to extend the distance between the two wiring patterns. Wiring structure for repair of semiconductor integrated circuits. 2. The wiring structure for repairing a semiconductor integrated circuit according to claim 1, wherein the detour portion of the adjacent wiring pattern is provided in the same layer as the adjacent wiring pattern. 3. The wiring structure for repairing a semiconductor integrated circuit according to claim 1, wherein the detour portion of the adjacent wiring pattern is provided in a layer different from the adjacent wiring pattern via a through hole. 4. The wiring structure for repairing a semiconductor integrated circuit according to claim 3, wherein the different layer is a layer above the layer of the adjacent wiring pattern. 5. Regarding two almost parallel adjacent wiring patterns,
Repair of a semiconductor integrated circuit, characterized in that a repair area is provided in a part of both wiring patterns by expanding the interval between the two wiring patterns, and the repair area is used for repair by changing the wiring after chip manufacturing. wiring structure. 6. A repair wiring method for creating a wiring pattern for repair after chip manufacturing of a semiconductor integrated circuit, in which wiring is first performed without considering the spacing between adjacent wiring patterns, and then a wiring pattern that can be repaired is created. Focusing on
It is checked whether there is a part where the interval between the wiring pattern and the wiring pattern adjacent to the wiring pattern is wider than a predetermined interval, and if the result of the check is negative, the interval between the wiring pattern adjacent to the wiring pattern is 1. A wiring method for repairing a semiconductor integrated circuit, comprising: providing a detour portion that makes the distance from the noted wiring pattern larger than the predetermined distance by changing the route. 7. A repair wiring method for creating a wiring pattern for repair after manufacturing a semiconductor integrated circuit chip, which includes: a) performing wiring without taking into account the spacing between adjacent wiring patterns; and b) creating a wiring pattern that can be repaired. c) for each of the registered wiring patterns, search for a wiring pattern adjacent to the wiring pattern, and d) for one of the registered wiring patterns, the distance between the adjacent wiring pattern is less than a predetermined interval. Check whether a wide area exists; e) If the result of the check is positive, register the area as a repair area; f) If the result of the check is negative, By changing the route of the adjacent wiring pattern at an appropriate location, a detour section is provided that makes the distance between the wiring pattern of interest larger than the predetermined distance, and the location is registered as a repair area. , g) A wiring method for repairing a semiconductor integrated circuit, characterized in that steps c) to f) are repeated for all the registered wiring patterns. 8. The check in step d) is performed on one of the registered wiring patterns from one end of the wiring pattern to the other end, sequentially for each location for each unit length. 7. The wiring method for repairing a semiconductor integrated circuit according to 7. 9. The method according to claim 7, wherein the registration result of the repair area is output to an output device after the steps e) and f) and/or after the step g). Wiring method for circuit repair. 10. The adjacent wiring patterns to be checked include not only wiring patterns in the same layer as the wiring pattern of interest, but also wiring patterns in layers above the layer, by projecting the wiring patterns in the upper layer onto the layer. 8. The wiring method for repairing a semiconductor integrated circuit according to claim 6, wherein the wiring method is taken into consideration. 11. The wiring method for repairing a semiconductor integrated circuit according to claim 6 or 7, wherein the detour portion is provided in the same layer as the adjacent wiring pattern or in an upper layer.