JPH02158246A - 4-phase phase modulation signal demodulator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is directed to quadrature phase modulation (Quad Phase Modulation).
ftKeying (hereinafter abbreviated as QPSK) signal and output from a voltage controlled oscillation (hereinafter abbreviated as vCO) circuit Background Art In recent years, digital signal transmission has become active in the communication field and the like. When transmitting digital signals, it is necessary to modulate and transmit the digital signals due to the transmission band limit of the communication path and self-clock regeneration on the receiving side, and one of the methods is QPSK signal. be.

The QPSK signal divides the digital signal to be transmitted into every 2 bits, and uses the four values represented by the 2 bits as 0', 90°, and 180° of the phase of the subcarrier signal used for transmission.
The subcarrier signal to be transmitted is 5=E-CO8(ωt+θ), where ω is the angular frequency θ of the subcarrier, which is expressed as O'or90°or180°or270'. However, on the receiving side, it is necessary to demodulate and reproduce the original digital signal from the subcarrier signal modulated by the QPSK method.

A conventional QPSK signal demodulator will be explained below based on FIG. 4. FIG. 4 is a block diagram of a conventional QPSK signal demodulator, in which 41 and 42 multiply the QPSK signal input to input terminal A by the reference phase signal output from the vCO circuit 38 and the modulation circuit 39. The output signals of the multiplier circuits 41 and 42 are sent to a comparator 35 via a low-pass filter (hereinafter referred to as LPF) 32, and are also sent to an adder 33. Subtractor 342 Multiplier circuit 4
Sent to 3. The outputs of the adder 33 and the subtracter 34 are connected to a multiplication circuit 44, and the outputs thereof and the output of the multiplication circuit 43 are connected to a multiplication circuit 45.

The output of the multiplication circuit 45 is transmitted to the error signal output circuit 36 and LP
It is connected to the VCO circuit 38 via F37.

Next, the operation of the QPSK signal demodulation device configured as described above will be explained.

First, the QPSK signal input to input terminal A is 5=E-
CO8 (ω is 10) It is expressed as (1).

The clock signal output from the 700 circuit is Cq=E,・
COS <ωt+ψ) ・・・・・・■π/2 phase modulated clock signal is Cq ” E +・5IN (ω is 1ψ) ・・・・
...It is expressed as (3).

The output of the multiplication circuit 41 is the output of the multiplication circuit 42.The output of the multiplication circuit 41.42 is passed through the LPF 32, and a digital value is demodulated and output from the comparator (compared with O) according to the value of θ-ψ. Masu.

Furthermore, the P and Q signals obtained by the above equations are multiplied by a multiplier circuit 43, and are also multiplied by an adder 33. It passes through a subtracter 34 and is multiplied by a multiplier circuit 44. Then...(8) (P-Q) (P+Q)=P2-Q'...
(9) becomes.

Next, the output obtained from the above equation is multiplied by the multiplication circuit 45, resulting in the phase difference (θ−
ψ), the output voltage becomes O at nπ/4, the loop is locked in this state, and the QP is quadrature phase modulated.
The SK signal is demodulated and output to the B and C output terminals.

Problems to be Solved by the Invention However, in the conventional configuration described above, the signals and reference phase signals handled are SIN waves and COS waves, so it is necessary to perform analog processing for multiplier circuits, adders, subtracters, LPF, etc. , the circuit cannot be configured unless the number of elements is increased or the power supply voltage is set to a high level to realize a multiplier circuit, etc.

In addition, external parts are required for the LPF, and QPSK in the latter stage
This has had problems such as not being able to be integrated with a digital processing section that processes demodulated digital signals.

The present invention solves the above conventional problems, and is a QPSK signal demodulator capable of demodulating a digital signal from a QPSK signal using a digital circuit and generating a phase comparison error signal between the QPSK signal and a reference phase signal. The purpose is to provide equipment.

Means for Solving the Problems To achieve this object, the QPSK signal demodulation device of the present invention is comprised of a digital circuit that demodulates and reproduces a digital signal and generates a phase comparison error signal between the QPSK signal and a reference phase signal. It also includes a first multiplication circuit, a data discrimination circuit, a second multiplication circuit, an adder, and an error signal output circuit.

Operation With the above configuration, demodulation and reproduction of digital signals and QP
To be able to generate a phase comparison error signal between an SK signal and a reference phase signal using a digital circuit, and to achieve reduction in circuit scale and integration with a digital signal processing section that processes demodulated and reproduced digital signals. Can be done.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a QPSK signal demodulator according to an embodiment of the present invention, and FIG. 2 is a specific circuit diagram of FIG. 1.

In FIG. 1, 11 is the QP input from input terminal A.
A first multiplier circuit that multiplies the SK signal and a reference phase signal output from the VCO circuit, and the first multiplier circuit 1
1 is subjected to data discrimination by a data discrimination circuit 12, and the output of this data discrimination circuit 12 is multiplied by the output of the first multiplication circuit 11 in a second multiplication circuit 11.
The outputs of the two second multipliers are added by an adder 15, and then sent to an error signal output circuit 15. vCO via LPF16
This becomes a control voltage for the circuit 17, and a reference phase signal is generated from the VCO circuit 17, which is subjected to π/2 phase modulation to generate a second reference phase signal.

As shown in FIG. 2, the first multiplication circuit 11 consists of a digital exclusive OR (FOR) gate 21 and an inverter 22.
The second multiplier circuit 13 is formed by a FOR 21 or an EOR 21 and an inverter 22.

Adder 16 is formed by an OR gate 24 . Further, the error signal output circuit 15 is formed of a flip-flop with reset 25, a human-powered N0R26, a P-channel MOS transistor 27, and an N-channel MO8 transistor 28. Furthermore, the modulation circuit 19 is formed by a 1/4 frequency divider circuit 29 and a flip-flop 23.

Next, the operation of the QPSK signal demodulator of this embodiment will be explained using the timing chart of FIG.

The timing chart in FIG. 3 is for the case where the QPSK signal is delayed by π/4 phase with respect to the reference phase signal Cq. As shown in the timing chart, the output of the first multiplier circuit is the signal of QPSKΦCq and Q
This becomes the signal of PSK■C9. This signal is latched by a flip-flop using C9 and C3 as clock signals. In this example, it is -H''. That is, output terminals B and C
Similarly, when the QPSK signal is lagging (3·π/4) with respect to the reference phase clock C1, L'' is output to output terminal B and H'' is output to output terminal C. When the phase delay is (5・π/4), “L” is output to the B and C output terminals, and if the phase is further delayed by (7・π/4), the output terminal B "H" is output to "H" and "L" is output to C, and 2-bit data is demodulated and reproduced for the four phase changes of QPSK.

When the phase delay is other than (n·π/4) (n is an odd number), the “L” level pulse width of the output signal of the adder 24 is
Since the output of the error signal output circuit 15 changes according to the amount of deviation from the phase lag (n·π/4), the width of the “H” pulse changes according to the amount of deviation from the phase lag (n·π/4). The width of the L-pulse is constant (n・π/4), which is integrated by the LPF 16 and the output voltage is used by the vCO circuit 17.
By controlling the output of the QPSK signal, a phase control loop can be constructed for the four phases of the QPSK signal. The output signal of the VCO circuit 17 is frequency-divided by (1/4) and its output is delayed by one clock of the clock of the VCO circuit 17 to generate a SIN wave, CO5-, with a phase shift of π/2.
Two reference phase signals corresponding to waves are generated.

As described above, according to this embodiment, the multiplication of the QPSK signal and the reference phase signal is performed using an exclusive OR (FOR) gate and an inverter, and the data discrimination circuit is implemented using a flip-flop. Demodulation of a digital signal from a QPSK signal and generation of a phase comparison error signal between the QPSK signal and a reference phase signal were all realized using a digital circuit.

This makes it possible to realize integration with the digital signal processing section and to reduce the number of external components.

Effects of the Invention According to the present invention, the first
By providing the multiplication circuit, the data discrimination circuit, and the second multiplication circuit, it is possible to demodulate the digital signal from the QPSK signal and generate a phase comparison error signal between the QPSK signal and the reference phase signal using only the digital circuit. , by reducing the LPF, external filter components (capacitors, resistors) can be reduced, and the first multiplier circuit and second multiplier circuit are configured with exclusive OR (EOR) gates and inverters. Many excellent effects can be obtained, such as the ability to significantly reduce the circuit scale.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the QPSK signal demodulation device of the present invention, FIG. 2 is a specific circuit diagram of the embodiment device of FIG. 1, and FIG. 3 is the operation of the circuit diagram of FIG. 2. FIG. 4 is a block diagram of a conventional QPSK signal demodulator. 11...First multiplication circuit, 12...Data discrimination circuit, 13...Second multiplication circuit, 14
... Adder, 15 ... Error signal output circuit, 16 ... LPF. 17... vCO circuit, 18... modulation circuit, A... input terminal, B... output terminal, C... output terminal, 21... Exclusive OR (EOR), 22... Inverter, 23...
... Flip-flop, 24 ... Logical sum (OR), 25 ... Flip-flop with reset, 26 ... 2-man power N0R127 ...
P channel MOS transistor, 28... N channel MOS transistor, 29... frequency dividing circuit, 32... LPF. 33...Adder, 34...Subtractor, 3
5...Comparator (comparator), 36...
...Error signal output circuit, 37...LPF, 38
... vCO circuit, 39 ... modulation circuit,
41 to 45...Multiplication circuit. Name of agent: Patent attorney Shigetaka Awano and one other person: Yusei Shirahai

Claims (5)

[Claims] (1) a pair of first multiplier circuits that perform multiplication of a quadrature phase modulation QPSK signal and a reference phase signal; and a pair of data discrimination circuits that determine a digital signal from the output of the first multiplier circuit; a pair of second multiplier circuits configured to multiply the output of the data discrimination circuit by the output of the first multiplier circuit; and a second multiplier circuit configured to multiply the output of the data discrimination circuit by the output of the first multiplier circuit; an adder that generates a phase error signal; an error signal output circuit connected to the adder; a voltage controlled oscillation circuit controlled via a low-pass filter by the output signal of the error signal output circuit; 1. A four-phase phase modulation signal demodulation device, comprising: a modulation circuit that performs π/2 phase modulation on a reference phase signal output from the circuit. (2) The four-phase phase modulation signal demodulation device according to claim (1), wherein the first multiplier circuit includes an exclusive OR gate and an inverter. (3) The four-phase phase modulation signal demodulation device according to claim (1), wherein the data discrimination circuit is a flip-flop. (4) One of the second multiplication circuits is an exclusive OR, and
2. The four-phase phase modulation signal demodulator according to claim 1, wherein one of the demodulators is comprised of an exclusive OR gate and an inverter. (5) The four-phase phase modulation signal demodulation device according to claim (1), wherein the adder is an OR gate.