JPH0219664B2 - - Google Patents

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention is based on MSK (Mini
-mum Shift Keying) This is related to the carrier wave regeneration circuit in the demodulation circuit of the signal synchronous detection method using Shift Keying.It is not limited to the MSK method, but is a modified method of MSK that performs various band restrictions that are considered as a group of MSK (GMSK). Gaussian Filtered
MSK) or similar phase-changing offsets
It can also be applied to demodulation circuits such as QPSK (OQPSK).

(Prior Art) Synchronous detection circuits for MSK signals are described in various documents. FIG. 1 is well known for its basic configuration example. In FIG. 1, 1 and 3 are phase detectors, and 2 and 4 are low-pass filters (LPF) that remove unnecessary components such as carrier components and noise outside the signal band. 5 is a 90° phase shifter, and 6 is a voltage controlled oscillator (VCO), which generates a carrier frequency synchronized with input 14 for synchronous detection. 7 is loop filter (FL)
Determine the loop bandwidth for phase locking. 8 and 9 are multipliers (MLT), 10 and 11 are judgment circuits (DEC), 12 is exclusive OR circuit (EX-OR),
13 is a timing synchronization circuit (CLK), and 15 is a demodulation output. The operation of these circuits is well known and will be briefly explained next. The phase detectors (DET) and LPF of 1 to 4 are used to demodulate the input signal, and at the same time the phase shift circuits of 5 to 9, VCO, FL,
Together with the two MLTs, it constitutes a phase locked loop (PLL). Also, EX of judgment circuit 12 of 10 and 11
-OR gate operates to determine information from the output of the LPF and obtain demodulated output 15.

Since the present invention relates to the configuration of the multiplication circuit (MLT) 8 of the phase-locked circuit as described above, the MLT
8 will be further explained.

In Figure 1, the output of MLT9 is the component of the input signal that is in phase with the output of VCO6, that is, LPF2.
Since it is the product of the output of the LPF 4 which is a component of the orthogonal input signal, it is given by the following equation for the MSK signal. [For example, see Reference (1) page 5 below] v _p (t) = A ² /8 sin (g _i nπt/T + 2θ _e ) where A is the amplitude of the input signal 14, and g _i is the modulation 2
value information (±1), T is the information bit length, and θ _e is the phase difference between the input and reproduced carrier waves.

The input of MLT8 is the above v _p (t) and the other
Input v _r (t) from CLK13, v _r (t) is 10,
11 and a clock whose phase is shifted by 90 degrees, it is expressed by the following equation.

v _r (t)=cos(πt/T) The multiplication circuit MLT8 performs these multiplications, and its output is as shown in the following equation.

v _e (t) = v _p (t) v _r (t) = A ² /8 sin (g _i πt/T + 2θ _e ) cos (πt/T
) = A ² /16 [sin {(g _i +1) πt/T+2θ _e } + sin {(g _i −1) πt/T+2θ _e }) Here, if the probability of g _i being +1 and -1 is equal, a loop If only this low frequency component is extracted by the filter 7, the following equation can be obtained.

v _e (t) A ² /16sin2θ _e As a result, a voltage v _e corresponding to the phase error θ _e is obtained, and the VCO 6 can be controlled by v _e to synchronize the carrier wave.

Since the multiplication circuits 9 and 8 perform multiplication of baseband signals with DC components, it is difficult to create a stable circuit using a normal analog circuit. Therefore
Either convert the outputs of LPF2 and LPF4 into a binary signal using OV as a threshold, or
Alternatively, a method is generally used in which the multiplier circuit is implemented as a digital circuit by converting the inputs of the phase detectors DET1 and DET3 into binary values. For binary signals, an EX-OR circuit can be used as a multiplier circuit. FIG. 2 shows in detail the circuit from the multiplier circuit 8 to the VCO 6 using this method.

In FIG. 2, 16 and 17 are binary signals of in-phase and quadrature components, respectively, which are input to the multiplier circuit 9 in FIG. 1, 18 is an EX-OR circuit that functions as the multiplier circuit 9, is an EX-OR circuit that functions as the multiplier circuit 8, 20 is a clock input, circuit 21 composed of resistors R1 and R2 and capacitor C1 is a loop filter corresponding to FL7, and 22 compensates for the DC component of the output from 19. 23 is a DC amplifier that doubles as voltage shift and DC voltage amplification for
This is the same VCO as VCO6.

FIG. 3 is a time chart of waveforms of various parts in FIG. 2. a shows the phase of the input signal (that is, the phase difference with the VCO output) along with the modulation data (same as 15 in Figure 1) shown in binary form at the top, b
is the input 16, c is the input 17, d is the output of the EX-OR circuit 18, e is the clock 20, f is the EX-OR
The outputs of the circuits 19 are shown respectively.

In these waveforms, solid lines indicate a state in which the output of the VCO matches the phase of the input carrier wave, and dashed lines indicate a state in which the phase is shifted.

As can be seen from the circuit in Figure 1 and the above explanation, b is at H level when the phase difference between the input and VCO 6 is 0 to π rad, and is at L level in other cases, and c is when the phase difference is -π/ When the signal is 2 to π/2, the signal is at H level, and at other times, it is at L level. The clock 20 is synchronized by the timing synchronization circuit 13 of FIG. 1 so as to have the timing shown in FIG. 3e. The fact that d and f are as shown in Figure 3 is EX-
This is clear from the theory of OR circuits. As shown in f, in the synchronized state, the low frequency component (average voltage) of the output waveform of 19 is the average value of the H level voltage and the L level voltage, but there is a phase error. The low frequency component is biased toward the H level or L level due to the phase difference between the two. Therefore, phase synchronization is achieved by passing this through a loop filter, shifting the voltage using a DC amplifier to match the center voltage of the frequency control input of the VCO 23, and inputting it to the VCO 23. However, the circuit shown in FIG. 2 has the advantage of being simple because the multiplier circuit can be realized by a digital circuit, but on the other hand, the input voltage (low frequency component) to the loop filter 21 in the synchronous state is It is the average value of level and L level,
It has the drawback of not being an OV. Next, this drawback will be explained in more detail.

As mentioned above, the average voltage in the synchronized state of the output of the phase difference detection circuit (18 and 19 in Fig. 2 constitute a phase difference detection circuit with two inputs 16 and 17) is the average value of the H level and L level. If it is, the following problems will occur.

(1) H of digital circuit (for example, TTL circuit)
The level changes depending on the power supply voltage. Therefore, the operation of the circuit is susceptible to fluctuations in the power supply voltage and noise in the power supply circuit, resulting in unstable synchronization and increased jitter in the reproduced carrier wave.

(2) If you want to increase the loop gain of the phase-locked circuit, it is necessary to DC amplify the phase difference detection output as shown in Figure 2, but in this case, the average voltage
It is necessary to perform a voltage shift to correct the deviation from OV, and this also becomes a factor that makes the synchronous operation unstable, similar to (1). Therefore, it is difficult to increase the loop gain.

(Specific Object of the Invention) In order to eliminate the above-mentioned drawbacks of the conventional circuit, the present invention provides a phase difference detection system in which the output voltage (average voltage) of the phase difference detection circuit in a synchronous state changes around OV. It provides a circuit.

(Structure and operation of the invention) FIG. 4 shows an improved circuit of FIG. 2 including a phase difference detection circuit according to the invention. 21,2 in Figure 4
2 and 23 are the same loop filters, DC amplifiers, and VCOs as in FIG. 2, and the others constitute a phase difference detection circuit. 16, 17, 18, and 20 also represent the same in-phase component input, quadrature component input, EX-OR circuit, and clock input as in FIG. 2, respectively. 24 is a clock buffer gate, 25 is an operational amplifier, and 26 is an analog switch, which shorts the positive phase input terminal of the operational amplifier 25 to ground or opens it.
This is done by input from the EX-OR circuit 18. Let resistance R4=R5=R6.

Next, the operation of the circuit shown in FIG. 4 will be explained. After passing through a buffer gate 24, the clock 20 is supplied to a resistor R3 via a capacitor C2. clock 20
As shown in Figure 3e, is a repeating rectangular wave with a duty of 50%, so the DC component is blocked by capacitor C2, and the waveform applied to resistor R3 is the average voltage.
At OV, it becomes a square wave with equal positive and negative voltage values. Next, when the switch 26 is closed and short-circuited to ground, the operational amplifier 25 operates as an inverting amplifier with a gain of 1 because R5=R6 since the positive phase input becomes OV. Conversely, when the switch 26 is disconnected from ground, the operational amplifier 25 has a positive phase input connected to R3.
Since the voltage is the same as the terminal voltage of , it operates as a common mode amplifier with a gain of 1. From the above, the circuit composed of the operational amplifier 25, analog switch 26, and C2, R3 to R6 operates as a multiplier circuit, and its output has a waveform similar to that shown in Figure 3f, and the DC component in the synchronous state is OV. The following output is obtained. Therefore, in this case, there is no need to perform a voltage shift in the DC amplifier 22, and a stable phase difference detection output can be obtained.

Note that even if the power supply voltage fluctuates, capacitor C2
Due to the DC cutoff caused by EX
-The output of the OR gate 18 is the analog switch 26
Since it is only used for opening and closing, the phase difference detection output remains stable without fluctuations due to power supply voltage.

(Effects of the Invention) By using the synchronous detection circuit according to the present invention in a demodulation circuit for MSK signals, etc., the following effects can be obtained, and a stable synchronous detection circuit with less jitter can be realized.

b) Since the output voltage in the synchronized state of the circuit is OV, the degree of freedom in designing each element that makes up the circuit, especially the VCO and DC amplifier, increases.

b) The output voltage of the circuit in the synchronous state is OV and is not affected by fluctuations in the power supply voltage or level fluctuations in the output voltage of the circuit or elements.

(References) (1) Murota, Hiraide: “GMSK for digital mobile communications
Modulation Method” Research and Practical Application Report Volume 32 No. 6 (1983
) Nippon Telegraph and Telephone Public Corporation.

[Brief explanation of drawings]

Figure 1 is an example of the basic configuration of a synchronous detection circuit, Figure 2 is an example of a specific circuit configuration of a part of Figure 1,
FIG. 3 is a diagram showing an example of waveforms of various parts in FIG. 2, and FIG. 4 is a diagram showing an example of an improved configuration of the circuit shown in FIG. 2 when the present invention is implemented. 1, 3... Phase detector, 2, 4... LPF, 5
...90° phase shifter, 6, 23... Voltage controlled oscillator (VCO), 7... Loop filter, 8, 9...
Multiplier, 10, 11...Decision circuit (DEC), 1
2, 18, 19...Exclusive OR circuit (EX-
OR gate), 13... Timing synchronization circuit (clock generation circuit), 14... Input signal, 15...
Demodulation output, 16, 17...18 inputs for each output of LPF2, LPF4, 21...Loop filter, 2
2...DC amplifier, 24...Clock buffer gate.

Claims (1)

[Claims] 1. Two phase detectors that generate detection outputs of the input digital signal and the in-phase output and the quadrature-phase output of the voltage controlled oscillator, respectively, a first multiplier circuit that multiplies the two detection outputs, and an output of the first multiplier circuit. a second multiplier circuit that multiplies the clock and the clock;
In the MSK signal synchronous detection circuit, which is configured with a loop filter and a DC amplifier, and supplies the output of the second multiplier circuit to the loop filter and the DC amplifier as a frequency control voltage of the voltage controlled oscillator, The multiplier circuit has an analog switch that is opened and closed by the output signal of the first multiplier circuit, and one input of the clock whose DC component is blocked by a capacitor, and which operates according to the opening and closing of the analog switch. A synchronous detection circuit for MSK signals, characterized in that it is configured with operational amplifiers that each switch to an in-phase amplifier and an inverting amplifier.