JPH02158290A - motion detection circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a motion detection circuit that determines whether a video signal is a moving image or a still image.Prior art FIG. 4 shows a conventional motion detection circuit. FIG. 2 is a configuration diagram of (first conventional example). In FIG. 4, 15 is a low-pass filter (LP
F), 16.21.22 is a frame memory (F.F) that delays the signal by one frame period.

M), 17.23 is a subtracter, 18.24 is an absolute value circuit,
19.25 is a threshold circuit that determines the magnitude relationship between the input signal and the threshold, 20 is a bypass filter (HPF), and 26 is a determination circuit that determines motion from the outputs of the two threshold circuits 19.25.

In the conventional motion detection circuit configured as described above, an NTSC signal is input from the terminal 14, and LPF15 and H
It is input to PF20.

The LPFI 5 passes the low frequency component of the NTSC signal, that is, the low frequency luminance signal, and inputs it to the FM 16.

The subtracter 17 subtracts the undelayed low-range luminance signal from the l-frame-delayed low-range luminance signal, and the absolute value circuit 18 obtains the absolute value of the output of the subtracter 17. Since the positions of the two signals separated by one frame period on the screen are the same, when the image is a still image, these two signals are exactly the same, and the output of the absolute value circuit 18 is "0". On the other hand, when there is movement in the image, the signals separated by one frame period are different, so that the absolute value circuit 18 obtains a signal other than "0". The threshold circuit 19 compares the output of the absolute value circuit 18 with a certain threshold value, and if the threshold value is smaller,
On the other hand, when the threshold value is larger, "0" is output as a still image, indicating that there is movement.

The HPF 20 outputs a high frequency video signal that is a mixture of a high frequency luminance signal and a carrier color signal. This high frequency video signal has two F and M
21 and 22 are input in sequence.

In the subtracter 23, the undelayed high frequency video signal is subtracted from the delayed high frequency video signal.

Since the phase of the carrier color signal is inverted for each frame, they are in phase when two frames apart. The output from the subtracter 23 is input to the absolute value circuit 24 and the threshold value circuit 25 in the same way as before.
The output from the threshold circuit 25 is "0" for a still image, and "1" for a moving image.

The determination circuit 26 outputs "1" when the output of the threshold circuit 19 or the threshold circuit 26 is "1".

That is, if motion is detected in either the low-frequency luminance signal or the high-frequency video signal, it is determined that there is motion, and "1" is output.

FIG. 5 is a block diagram of another conventional motion detection circuit (second conventional example). In FIG. 5, 29 is a 262H delay that delays by 262 lines, 30.33 is a subtracter, 32 is F,
M, 31.34 is an absolute value circuit, and 35 is a threshold value circuit.

In the conventional motion detection circuit configured as described above,
When an NTSC signal is input from terminal 28, subtraction a30
, the undelayed signal is subtracted from the 262-line delayed signal. Since the phase of the carrier color signal of the signal 262 lines before is the same, the output from the subtracter 30 includes a two-dimensional vertical signal difference and a signal difference in the case of a moving image.

This difference signal is input to the absolute value circuit 31, and its absolute value is obtained. The output of the absolute value circuit 3-1 is input to the frame memory 32, and a subtracter 33 obtains the difference between the signal delayed by one frame period and the signal not delayed. The difference signal that is the output of the subtracter 34 is input to the absolute value circuit 34 to obtain its absolute value, and is input to the threshold circuit 35.

FIG. 2 shows the relationship between the sample points of each field and the phase of its subcarrier. In FIG. 2, SO is the sample point of the n field, and SL and 82 are the sample points of the n+1 field. Sl is one line above S2 on the screen. Further, s3 is a sample point of field n+2, and S4 is a sample point of field n+3. The direction of the arrow at each sample point indicates the phase of subtransport, and SO
and 81 are in phase with each other, and S2. S3. S4 are also in phase with each other, but out of phase with SO.

When the signal inputted from the terminal 28 is a still image, the difference signal output from the subtracter 30 is divided into 83 and 8 in FIG.
4 and shows only the difference in the vertical signal in two dimensions. Therefore, in the case of a still image, this difference signal in two dimensions will be the same in the next frame (the difference between So and 81). ), the output from the subtracter 33 is "0". Also,
If the signal input from the terminal 28 is a moving image, the subtracter 3
The difference signal from 0 includes vertical difference and movement information in two dimensions, and becomes a difference signal of a different picture in the next frame, so the output from the subtracter 33 does not become "0".

Problems to be Solved by the Invention However, when a pattern of vertical stripes as shown in FIG. 3(A) moves in the horizontal direction, at a certain speed, the striped pattern of the n field and the striped pattern of the n+2 field are exactly reversed. This state is shown in detail in FIG. 3(B), which shows sample points in the horizontal direction of fields n, n+1, n+2, and n+3. As shown in the n field, the vertical stripe pattern repeats every 4 white and black sample points, and when two sample points are moved horizontally in one field, the white and black of the n field are reversed in the n+2 field. It becomes a pattern. Further, four sample points located at the same horizontal position in each field are given names 801 to S34 as shown in the figure.

When this signal is input to the motion detection circuit of the first conventional example (Fig. 4), since the vertical striped signal is only a high frequency component, the LPF
The output of 15 becomes "0" and motion detection must be performed using only the output of HPF 20. However, as shown in Figure 3 (B), this signal is inverted in one frame, so signals two frames apart are in phase. Become. Therefore, the output from the subtracter 23 becomes "0", and this signal is erroneously determined to be a still image.

Moreover, this signal is the motion detection circuit of the second conventional example (Fig. 5).
, the subtracter 30 inputs 3 of n+3 fields.
32 and S22 of field n+2 are input, since these two sample points are in phase, the output of the subtracter 30 becomes "0", and the output from the frame memory 32 becomes "n+1".
This is the absolute value of the difference between field S12 and field n SO2 and is also "0", so the output of the subtracter 33 is also "0". S3 of n+3 field in subtracter 30
When 3 and 323 of the n+2 field are input, the output of the subtracter 30 becomes a certain value because these two sample points are in opposite phases. However, the output of F and MB2 is also 313 and SO3
Since this is the absolute value of the difference between The signal is incorrectly determined to be a still image.

As described above, the conventional motion detection circuit has a problem in that when a signal as shown in FIG. 3 is input, it is incorrectly determined to be a still image.

Means for Solving the Problems The present invention is a motion detection circuit characterized by comprising a polarity determination circuit that checks the polarity of a pixel of interest, a pixel 262 lines before, and a pixel one frame before.

Operation The present invention is configured as described above, so that even if the image is a still image, if the absolute value of the difference value between signals separated by one frame period is not greater than a certain value, in other words, the conventional motion detection circuit will freeze the moving image. Even if it is mistakenly determined to be a picture, it can be determined correctly.

Embodiment In the following, a motion detection circuit according to an embodiment of the present invention will be described.
This will be explained in detail with reference to FIGS.

FIG. 1 is a block diagram of a motion detection circuit in this embodiment. In Figure 1, 2 is 262H, which delays 262 lines.
Delay, 3 is a 263H delay that delays by 263 lines, 4 is a polarity judgment circuit, 5 is an adder, 6 is a frame memory, 7 is a subtracter, 8 is an absolute value circuit, 9 is a threshold circuit, 10
1 is an AND circuit, 11 is an OR circuit, and 12 is a smoothing circuit.

When an NTSC signal is input from terminal 1 in the motion detection circuit configured as above, one of the signals is 262H.
Delay 2, 263H and delay 3 are input in sequence and delayed by exactly one frame period.

The adder 5 obtains the sum of the signal G3 delayed by one frame and the signal G1 not delayed. This added value is further input to a frame memory 6, and a subtracter 7 obtains a difference value between the delayed added value and the undelayed added value. If the input signal is a still image, the signal G1 separated by one frame period
．． Since the phase of the subcarrier of G3 is inverted, adder 5
The output becomes a luminance signal. If the input signal is a still image, the brightness signal one frame before and the current brightness signal are the same, so the output of the subtracter 7 will be "0". If the input signal is a moving image, the output of the adder 5 will be "0". , motion information is also added, and since the picture one frame before and the current picture are different, the level of the luminance signal is also different, and the output of the subtracter 7 will not be "0".The output of the subtracter 7 will be the absolute value circuit 8 When the output of the absolute value circuit 8 is smaller than a certain threshold value, the threshold value circuit 9 determines that the image is a still image and outputs "0". Further, when the output of the absolute value circuit 8 is larger than a certain threshold value, it is determined that it is a moving image and outputs "1".

The polarity determination circuit 4 receives the input signal G1, the signal G2 from 262H before, and the signal G3 from one frame before. If 83 of the n+2 field in FIG. 2 is the input signal G1, the output G2 of the 262H delay 2 is 82, and 26
Output G3 of 3H delay 3 becomes SO. When the input signal is a still image, So, S2. The phase of the subcarrier in S3 is that S2 and S3 are in phase as shown in FIG.
SO and 83 are in opposite phase. Set the polarity of input signal G1 to sig
n (Gl), the polarity of the signal G2 262 lines ago is set to st
gn (G2), the polarity of the signal G3 one frame before is s
ign (G3), the polarity determination circuit 4 outputs the following calculation result.

(sign(Gl) EXORsign(G3)l
AND (sign(Gl) EXORsig
n(G2)1 Therefore, even though SO and 83 in FIG. 2 are in opposite phases, if S3 and 82 are in phase, the polarity determination circuit 4 does not determine that it is a moving image and outputs "0". Output.

When the signal shown in Figure 3 is input to the above motion detection circuit, the phase of this signal is inverted every frame, so the adder 5
The output will always be somewhere between white and black. Then, the output of the subtracter 7 becomes zero, and the threshold circuit 9 determines that it is a still image and outputs "0".

Input signals Gl, G2 . G3 is S32. of FIG. 3(B). S22. If S12, S
32 and S12 are in opposite phases, but S22 and 332 are in the same phase, so the polarity determination circuit 4 does not determine that it is a moving image and outputs "O".
”.In addition, the input signal Gl of the polarity determination circuit 4,
G2. G3 is S33. in FIG. 3(B). S23.
In the case of S13, S33 and S13 are in opposite phase and S33
and S23 are also of opposite phase, so the polarity determination circuit 4 determines that it is a moving image and outputs "1".

In this way, when the signal shown in Fig. 3 is input, the polarity determination circuit 4 repeatedly outputs "1" and "0" every two sample points.Since the output of the threshold circuit 9 is always zero, the AND circuit The output of 10 repeats "1n" and "0" every two sample points, and the output of OR circuit 11 is the same. The smoothing circuit 12 examines the ratio of "0" and "1" in the two-dimensional area, and determines that it is a still image if the number of "0" is greater than a certain number.When the signal shown in FIG. ” and “1” are 50/50, so it is determined that it is a video.

As mentioned above, 262H delay 2, 263H delay 3, polarity determination circuit 4, AND circuit 10, and OR circuit 11
By using this, it is possible to reduce misjudgments in motion detection.

The present invention can be configured in various ways other than those shown in the above embodiments.

For example, 262H delay 2.263 in the above embodiment
The portion consisting of the H delay 3, polarity determination circuit 4, AND circuit 10, OR circuit 11, and smoothing circuit 12 is
A similar effect can be obtained by adding it to the motion detection circuit of the conventional example or the motion detection circuit of the second conventional example.

In addition to the motion detection circuit of the first conventional example, the above-mentioned 26
Assuming that the input of the 2H delay 2 is the terminal 14 of the first conventional example,
Instead of the output of the threshold circuit 9, the output of the determination circuit 26 of the first conventional example may be used.

To add to the motion detection circuit of the second conventional example, the above-mentioned 26
The input of the 2H delay 2 is the terminal 28 of the second conventional example, and the output of the threshold circuit 9 is replaced by the threshold circuit 3 of the second conventional example.
The output of No. 5 may be used.

As described in detail, according to the present invention, even if the conventional motion detection method determines that the image is a still image, the sample point of interest, the sample point of the previous field, and the sample of the previous frame can be Misjudgment can be prevented by checking the phase of three sample points, which has a great practical effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a motion detection circuit according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing the phase of subcarriers of pixels in each field, and FIG. 3 is an explanatory diagram showing the characteristics of a certain moving image. FIG. 4 is a block diagram of a first conventional motion detection circuit, and FIG. 5 is a block diagram of a second conventional motion detection circuit. 1...Input terminal, 2...262H delay, 3...
・263H delay, 4... Polarity judgment circuit, 5...
Adder, 6...Frame memory, 7...Subtractor, 8
... Absolute value circuit, 9. Threshold circuit, 10.. AND circuit, 11.. OR circuit, 12.. Smoothing circuit. Name of agent: Patent attorney Shigetaka Awano (E)

Claims (1)

[Claims] A means for obtaining a pixel 262 lines before a pixel of interest and a pixel one frame before by using a discretized NTSC signal as an input signal, and polarity of the pixel of interest, a pixel 262 lines before, and a pixel one frame before. Check the pixel of interest and 26
The polarity of the pixel two lines before is opposite and the pixel of interest is 1
a polarity determination circuit that outputs a polarity video signal when the polarity of a pixel before a frame is opposite; an addition means for calculating an added value between the pixel of interest and the pixel from one frame before; and this addition value and one frame. subtraction means for calculating the difference value between the previous addition values; comparison means for outputting a threshold signal when the absolute value of this difference value is greater than a certain value; and a logic circuit that determines that there is movement in two cases: when the polarity video signal is not detected and the polarity video signal is output.