JPH02159014A - Method of and apparatus for producing data for charged particle beam lithography - Google Patents

Abstract

PURPOSE:To establish high speed data conversion by simultaneously converting a plurality of pattern data each in a block unit to drawin data by parallely operating a plurality of pipe line-constructed processing units for data conversion. CONSTITUTION:A whole function is divided into three functions each processed by an exclusive cluster (processor group). In each cluster, a plurality of processor elements(PE) each a several K byte order local memory are coupled with each other through an about 1 M bites/sec data link. Processing among the clusters are executed in a pipe line manner. A distribution cluster 10 distributes pattern data in a block unit transferred from a host computer to a parallel processing unit composed of a plurality of figure computation clusters 20 (201-20N). The figure computation cluster 20 applies figure computation processing to the block data supplied from the distribution cluster 10, and outputs a result to a merge cluster 30. The merge cluster 30 receives a processed result from the figure computation cluster 20 and outputs block data in one unit.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Field of Application) The present invention is directed to a charged beam lithography data generator that executes lithography data creation processing (data conversion) for a charged beam lithography device in parallel at high speed. This invention relates to a production method and a production device.

(Prior Art) Conventionally, data conversion processing for creating lithography data (EB data) acceptable to an electron beam lithography system from LSI pattern data was often performed by software using a general-purpose computer such as a minicomputer. It has been. Furthermore, in order to cope with large-scale data, for LSIs such as memories in which the same pattern appears repeatedly, a method is used in which data processing is performed only on repeating units and processing is omitted for the rest.

However, due to the recent increase in LSI integration, E
The processing time required for data conversion to B data is becoming enormous. For example, there are reports that it takes several days to a week for calculations and computer processing in advanced memory devices. This is the case even with memory patterns that can speed up processing by using repetitive information, but the problem becomes even more serious in patterns with less regularity, such as logic circuits and gate arrays, where it is impossible to speed up processing using this method. The situation is as follows.

Therefore, it was necessary to develop a new means for speeding up data conversion processing that is also effective for such irregular LSI patterns. Furthermore, this requirement has become an essential issue in putting electron beam lithography systems into practical use for LSIs that will become larger and larger in the future.

(Problems to be Solved by the Invention) As described above, in order to put an electron beam writing apparatus into practical use, it has become necessary to create EB data from LSI pattern data at high speed.

Furthermore, this problem is not limited to electron beam lithography apparatuses, but also applies to ion beam lithography apparatuses.

The present invention has been made in consideration of the above-mentioned circumstances, and its purpose is to be able to create lithography data acceptable to a charged beam lithography system from LSI pattern data at high speed, and to improve lithography throughput, etc. It is an object of the present invention to provide a method and a device for creating data for charged beam drawing that can contribute to the improvement of the present invention.

[Structure of the Invention] (Means for Solving the Problems) The gist of the present invention is to convert block-based pattern data into drawing data at high speed through parallel processing.

That is, the present invention divides a predetermined data space of LSI pattern data into blocks of small areas that have no correlation with each other, and converts the pattern data of each divided block into writing data acceptable to a charged beam writing apparatus. In the method for creating data for beam writing, a plurality of processing units with a pipeline configuration, each consisting of a plurality of processors that perform different processes connected in series, are used to sequentially process pattern data in blocks transferred from a host computer into one of the In this method, the pattern data is transferred to a processing unit, and each processing unit is operated in parallel to convert the pattern data into drawing data.

More specifically, data conversion processing in units of blocks is performed in parallel by multiple processing units in a pipeline configuration in which multiple stages of processors each having at least two input/output terminals or communication ports corresponding to the input/output terminals are arranged. To operate and execute the pattern data in block units to the processing unit, a plurality of processors having the same characteristics as described above are connected in cascade using at least one input/output terminal, and a host computer is connected to at least one processor. Transferring the transferred block-by-block pattern data to the next processor one after another, and transferring the block-by-block pattern data to the processing unit connected to the remaining input/output terminal in response to a request from the processing unit. done by.

Further, the present invention provides a charged beam writing data creation device for performing the above conversion process, in which a plurality of processors performing different processes are connected in series, and a pipe converts pattern data in units of blocks into writing data. A parallel processing unit in which N line-configured graphical operation clusters are arranged in parallel, and N processors that temporarily hold pattern data in block units are connected in series, and each processor is connected to each graphical operation cluster of the parallel processing unit. a distribution cluster that is connected to each other and that sequentially transfers block-by-block pattern data transferred from the host computer to the next processor or one graphic operation cluster of the parallel processing unit; and a distribution cluster that temporarily holds block-by-block drawing data. N processors are connected in series, and each processor is connected to each graphic operation cluster of the parallel processing unit, and drawing data in units of blocks converted by each graphic operation cluster of the parallel processing unit is synthesized. A merge cluster to be transferred to the outside is provided.

(Function) According to the present invention, by operating a plurality of pipeline-configured processing units in parallel to perform data conversion, it is possible to simultaneously convert a plurality of block-based pattern data into drawing data. This can significantly reduce the time required for data conversion. Therefore, data conversion can be performed at high speed even for non-regular LSI patterns, contributing to improvement of drawing throughput and the like.

(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

In the parallel data conversion process according to this embodiment, black and white inversion (N
The goal is high-speed processing of logical operations such as OT), overlap removal (OR), and decomposition operations such as area division and polygon division. In these processes, if the data space is cut into meshes (blocks) of appropriate size, it is possible to process each block independently.

(2) Even if the output order of processing results changes, it can be easily logically reconfigured by adding identification numbers to blocks.

There is a characteristic that Taking these characteristics into consideration, the configuration of this parallel data conversion processing system was decided as shown in FIG.

FIG. 1 is a block diagram showing a schematic configuration of an electron beam lithography data creation apparatus according to an embodiment of the present invention. The overall functions are divided into three parts, and each function is processed by a dedicated cluster (group of processors). That is, distribute the data distribution (D)
In the cluster 10, a plurality of graphic operations (P) clusters 20 (20+ to 2ON) process graphic operations, and the collection of processing results is processed in a merge (M) cluster 30. In each cluster, a plurality of processor elements (PEs) having local memories on the order of several hundred bytes are connected by data links on the order of IM bytes/see. Furthermore, processing between clusters is executed in a pipeline manner.

The distribution cluster 10 distributes block-based pattern data transferred from the host computer to parallel processing units made up of a plurality of graphic operation clusters 20. Data distribution is performed in a manner such that PEs that receive requests from the graphical operation cluster 20 transfer data in blocks. If there is no request, it is postponed to the next PH in order to respond to requests from other graphic operation clusters 20. If the next PE is full, have a new request for the graphics operation cluster 20, or - the next PE is full.
wait until it becomes vacant. In this way, it serves to supply pattern data of block data so that the load on each graphic operation cluster 20 is approximately equal.

The graphic operation cluster 20 performs graphic operation processing on the block data supplied from the distribution cluster 10 and outputs the result to the merge cluster 30.

As shown in the figure, there are a plurality of graphic operation clusters 20, which operate in parallel. Furthermore, processing inside the cluster is also a pipeline. Each PE constitutes a pipeline stage, and communicates with the previous and subsequent PEs and performs graphic arithmetic processing within the PE in parallel.

Data is moved in blocks between pipe stages. In the graphic operation cluster 20, throughput is limited at the stage that takes the longest processing time. For this reason, it is necessary to divide the processing so that the processing time is equal at each stage.

The merge cluster 30 receives processing results from the graphic operation cluster 20 and outputs block data as one unit. Each PE of the merge cluster 30 is a graphic operation cluster 20
Receiving block data from PE and transferring it to the next PE are performed in parallel. Normally, the output light of the merge cluster 30 is a large-capacity magnetic disk device or the like, and the speed is relatively low. however,
Various methods can be considered to speed up this process, so even if we assume that the transfer from the merge cluster 30 does not become a bottleneck this time, it will not affect the effectiveness of the present invention in any way.

Next, the operation of the apparatus configured as described above will be explained using simulation and analytical evaluation.

As already mentioned, in this parallel conversion processor, pipeline processing is also performed between each cluster for distribution 9 graphic operations and merging. Therefore, the total data processing time for the TD...D cluster (to), the total data processing time for the TP...P cluster (tp), and the total data processing time for the TM...M cluster (tM) (however, The processing time per block is shown in parentheses), and the total processing time T is as follows: T intestine TD+tp+tM (8). That is, in order to obtain maximum throughput, T. +
All you have to do is find a condition that minimizes iP+tM.

Note that TD is a quantity that also depends on tP*iM.

Below, TD and tp are calculated based on the processing speed of the merge cluster 30.
The results of evaluating the performance of the distribution cluster 10 and the graphic operation cluster 20 under the condition that there are no restrictions are shown below. The performance of the distributed cluster 10 was evaluated using a software simulator. In the simulator, block data abstracted in terms of data volume, processing time, distribution thereof, etc. is input and characteristics are evaluated.

In the simulation, the optimal number of PEs in the distribution cluster 10 and the optimal number of buffers within the PEs were determined based on the data distribution method among PEs in the distribution cluster 10. condition is,
The transfer rate between PEs in the distribution cluster 10 and the transfer rate to the graphic operation cluster 20 were I M B /see, the average amount of block data transferred from the host was 640B, and the number of input blocks was 1000. Graphic operation cluster 2
Measurements were made by varying the time (ξ) required for one block of data (pattern data in block units) to pass through one stage of the pipe stage.

We measured how the throughput of the distribution cluster 10 changes with ξ. A method (Method 1) in which block data transfer ends at the last PE (the rightmost PE in Figure 1), and a method (Method 1) in which the block data transfer ends at the last PE (the rightmost PE in Figure 1).
A comparison was made with the method of refluxing to H (method 2).

In Figure 2, the number of PEs in the cluster (n PH) is lO1, the number of buffers (nB) is 3, and ξ is 0.2 to 200 m5ec.
/ This is the result of changing the block. Thrubutt is 1
/ξ, but both increase in proportion to 1/ξ-100(ξ-
It saturates at about 10m5ec/block). Under these measurement conditions, the graphs of Method 1 and Method 2 almost overlap over the entire area, and no significant difference is observed between the two methods. For this reason, subsequent measurements were performed using method 1.

Next, changes in the throughput of the distribution cluster 10 depending on the number of PEs were investigated. The results are shown in FIG. Here, nB = 3, ξ-20, 50° 2005 sec/block. When ξ-20, the throughput increases as the number of PEs increases, but n Pl! It reaches a peak around -40 and has no effect beyond that point. On the other hand, when ξ-50, n PE"" up to 100, and when ξm200, n p
It has the effect of parallelization up to FL-200. In other words, the smaller ξ is, the greater the effect of increasing nPE is.

FIG. 4 shows the distribution cluster 10 according to the number of buffers in PE.
We investigated the changes in the throughput. Here, n
When increasing 9, the throughput also increases, but it saturates at n, 83 for ξ-5 to 55, and saturates at nB-2 under other conditions. The reason for the saturation is considered to be that the processing speed of the graphic operation cluster 20 is slower than the transfer speed of the data link.

This is also clear from the fact that the throughput at saturation is almost inversely proportional to ξ.

From the above simulation results, it is sufficient that the number of PE buffers in the distribution cluster 10 is 3 and the number of PEs is about 40 under the expected processing conditions for EB data conversion. In that case, a throughput proportional to 1/ξ, ie, the pipeline speed of the graphics operation cluster 20, is obtained in the distribution cluster 10.

In addition, the pipeline processing of the graphic operation cluster 20 was modeled to evaluate the throughput.

For each graphic operation cluster 20, the number of vibrator stages is n.
, the inter-PE communication speed is τ, the number of blocks processed in a cluster is m, and the processing time for one block is σ. At this time, the time chart of the processing in each graphic operation cluster 20 is as shown in FIG. In the figure, it is assumed that each PE is equipped with an input and output buffer and can simultaneously execute communication with the previous and subsequent PEs.

As shown in FIG. 5, the last, m-th block is PE
, and before leaving the graphic operation cluster 20,
It must pass through (n-1) vibration stages. Therefore, the processing time TP of the graphic operation cluster 20 is m
As the sum of the time required for 1 block to pass through PE and the time required for 1 block to pass through (n-1) stages of vibes, Tp = (m+n-1) (σ/n+r) -(2)
It can be expressed as Since m, σ, and τ remain unchanged with respect to the number of PEs n, the n that minimizes TP is n-(m-1)σ/τ (3),
At this time, the processing time T, -a+ (m-1)r+2 (m-1)ra-
(Sh(m-1)r+J71 2 (4) is obtained.

Next, the device of this embodiment will be explained by applying it to data conversion processing using an actual LSI pattern.

Consider black and white inversion processing for a pattern with a data amount of 5 MB and a number of 500,000 figures. If this is processed on a large computer with a processing speed of 15 old PS, it will take 85 seconds of CPU time. this,
When processed on a virtual memory super minicomputer, the processing time is 21 minutes and 20 seconds. As an elemental processor of the present invention, for example, a processor Trans from Inmos (UK) is used.
puter; processing capacity 2 old PS, data link speed I MB/see.

It is assumed that main memory (~2MB) is used. Let us consider a case where a graphic operation cluster 20 is constructed using this processor and 10 processors are operated in parallel.

(However, the processing capacity in parallel with link transfer is 1.5MIP.
). The above data is 10.000
When divided into blocks and processed, a −128m5
ec, m -1000 Also, since the average amount of data per block is 500B, r -0,5 msec The processing time under this condition is shown in FIG. If a signal type operation cluster is composed of 10 PEs, Tp = 13.4 sec from the above equation (2). At this time, ξ-128710+0.5-13.3 (msec/B O-/ri), so 1/ ξ-75 (block/5ee) From Figure 2, the throughput of the distribution cluster 10 is 340K.
B/see, T, -5M B/
340 K B -14,8 (see). By the way, to process the last block, t, = 128 + 0.5XlO-13
Since it takes 3 (msec), under these conditions, the black and white inversion process can be processed in about 15 seconds.

Next, when the number of PEs that minimizes the processing time in the graphic operation cluster 20 is calculated using the above equation (8), it becomes n -505, and the processing time T p = l/13 sec is obtained from the above equation (4). It will be done. Also, at this time ξ-1281505+0.5=0.8 (msec/
block) Therefore, the throughput of the distribution cluster 10 is determined from FIG. 2 to be approximately IMB/see, and T o -5M
B/IM B-5 (see). Also,
Similarly, t p = 1281505+ 0.5X 505-2
53 (mscc) Therefore, under this condition, black and white inversion processing can be performed in about 5 seconds.

(Thus, according to the present embodiment, by operating a plurality of pipelined graphic operation clusters 20 in parallel and converting block-by-block pattern data into drawing data at high speed through parallel processing, block-by-block pattern data is can be converted into drawing data at the same time, which greatly reduces the time required for data conversion.In addition, the overall throughput can be reduced as long as the processing part that collects the results is not rate-limited. As a result of evaluation using simulation and analytical means, it was 1.5 on the 15 old PS large-scale computer.
The black and white reversal process, which takes 21 minutes on a super minicomputer,
It has been demonstrated that the time can be shortened to about 15 seconds. in this case,
The total number of required PHs is 120, and existing graphics calculation software can be used except for the parallel processing section.

Therefore, the cost of developing a two-parallel processor can be significantly reduced by using a chip such as the aforementioned Transputcr, compared to the case of using a conventional large-scale computer, and higher-speed data conversion can be achieved.

Furthermore, since this embodiment does not use pattern repetition, it is extremely effective in high-speed conversion processing of irregular patterns.

Note that the present invention is not limited to the embodiments described above. For example, the target data space may be a unit (one main field or subfield) that is drawn during one step and repeat in a step and repeat type electron beam drawing apparatus. Furthermore, in an electron beam lithography apparatus using a continuous stage movement method, a unit (one frame) of lithography during one continuous movement of the stage may be used. Further, when the LSI pattern data is expressed hierarchically, the data space may be a constituent unit of one layer (not limited to the lowest layer) that is hierarchically expressed. Furthermore, when the electron beam lithography apparatus is of a two-stage deflection type, the data for each block may be set to about jp corresponding to one of the deflection areas. Moreover, it goes without saying that the present invention can be applied not only to electron beam lithography apparatuses but also to ion beam lithography apparatuses. In addition, various modifications can be made without departing from the gist of the present invention.

[Effects of the Invention] As detailed above, according to the present invention, the time required for data conversion can be significantly reduced by operating a plurality of pipeline-configured processing units in parallel to perform data conversion. .

Therefore, data conversion can be performed at high speed even for irregular LSI patterns, and the drawing throughput can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic configuration of an electron beam lithography data creation apparatus according to an embodiment of the present invention, FIG. 2 is a characteristic diagram showing changes in the throughput of the distribution cluster depending on the processing speed of the graphic operation cluster, and FIG. The figure is a characteristic diagram showing the change in the throughput of the distribution cluster depending on the number of PEs, Figure 4 is the characteristic diagram showing the change in the throughput of the distribution cluster depending on the number of buffers in the PE, and Figure 5 is the time diagram showing the processing status in the graphic operation cluster. The chart in FIG. 6 is a characteristic diagram showing changes in throughput of distribution clusters and graphic operation clusters depending on the number of PEs in black-and-white inversion processing. 10...Distribution cluster, 20 (20+~2ON)...
・Graphic operation cluster (processing unit) 30... Merge cluster, PE... Processor element. Applicant's Representative Patent Attorney Takehiko Suzue 1st 6th Ward

Claims (4)

[Claims] (1) Charged beam lithography that divides a predetermined data space of LSI pattern data into blocks of small areas that have no correlation with each other, and converts the pattern data of each divided block into lithography data that is acceptable to a charged beam lithography system. In the method of creating data for , a pipeline configuration consisting of multiple processors connected in series that perform different processes is used, and the block-by-block pattern data transferred from the host computer is sequentially processed by one of the processing units. 1. A method for creating charged beam drawing data, the method comprising: transferring the pattern data to a computer, and converting the pattern data into drawing data by operating each processing unit in parallel. (2) The data space is a unit of writing during one step and repeat in a step-and-repeat type electron beam lithography system, or a unit of writing during one continuous stage movement in a stage continuous movement type electron beam lithography system. 2. The method of creating charged beam drawing data according to claim 1, wherein the unit is a unit of data. (3) An identification number is attached to the block-by-block pattern data, so that the block-by-block drawing data output from the processing unit in no particular order can be logically recombined. How to create data for charged beam lithography. (4) Charged beam lithography that divides a predetermined data space of LSI pattern data into blocks of small areas that have no correlation with each other, and converts the pattern data of each divided block into lithography data that is acceptable to a charged beam lithography device. In the data creation device, parallel processing is performed in which N graphic operation clusters are arranged in parallel in a pipeline configuration in which multiple processors that perform different processes are connected in series and convert pattern data in units of blocks into drawing data. unit, and N processors that temporarily hold pattern data in block units are connected in series, and each processor is connected to each graphic operation cluster of the parallel processing unit, and the pattern data in block units is transferred from the host computer. A distribution cluster that transfers data one after another to the next processor or one graphic operation cluster of the parallel processing unit, and N processors that temporarily hold drawing data in units of blocks are connected in series, and each processor is connected to the parallel processing unit. and a merge cluster that is connected to each of the graphical operation clusters of the parallel processing unit and that combines the block-by-block drawing data converted by each of the graphical operation clusters of the parallel processing unit and transfers it to the outside. A device that creates data for charged beam lithography.