JPH0215960B2 - - Google Patents
Info
- Publication number
- JPH0215960B2 JPH0215960B2 JP56063004A JP6300481A JPH0215960B2 JP H0215960 B2 JPH0215960 B2 JP H0215960B2 JP 56063004 A JP56063004 A JP 56063004A JP 6300481 A JP6300481 A JP 6300481A JP H0215960 B2 JPH0215960 B2 JP H0215960B2
- Authority
- JP
- Japan
- Prior art keywords
- data
- output
- block
- circuit
- blocks
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56063004A JPS57179997A (en) | 1981-04-25 | 1981-04-25 | Semiconductor memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56063004A JPS57179997A (en) | 1981-04-25 | 1981-04-25 | Semiconductor memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57179997A JPS57179997A (en) | 1982-11-05 |
| JPH0215960B2 true JPH0215960B2 (de) | 1990-04-13 |
Family
ID=13216735
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56063004A Granted JPS57179997A (en) | 1981-04-25 | 1981-04-25 | Semiconductor memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57179997A (de) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0612640B2 (ja) * | 1984-08-30 | 1994-02-16 | 三菱電機株式会社 | 半導体記憶装置 |
| JPS6159698A (ja) * | 1984-08-30 | 1986-03-27 | Mitsubishi Electric Corp | 半導体記憶装置 |
| DE3583493D1 (de) * | 1984-12-28 | 1991-08-22 | Siemens Ag | Integrierter halbleiterspeicher. |
| ATE51316T1 (de) * | 1984-12-28 | 1990-04-15 | Siemens Ag | Integrierter halbleiterspeicher. |
| JP2508629B2 (ja) * | 1985-02-28 | 1996-06-19 | 日本電気株式会社 | 半導体メモリ |
| JPS61292299A (ja) * | 1985-06-18 | 1986-12-23 | Toshiba Corp | オンチツプメモリテスト容易化回路 |
| JPS62170094A (ja) * | 1986-01-21 | 1987-07-27 | Mitsubishi Electric Corp | 半導体記憶回路 |
| JPS6446300A (en) * | 1987-08-17 | 1989-02-20 | Nippon Telegraph & Telephone | Semiconductor memory |
| EP0462743A1 (de) * | 1990-06-20 | 1991-12-27 | AT&T Corp. | Verfahren und Apparat zur Verdichtung von Ausgabedaten |
| US5959911A (en) * | 1997-09-29 | 1999-09-28 | Siemens Aktiengesellschaft | Apparatus and method for implementing a bank interlock scheme and related test mode for multibank memory devices |
| JP4540137B2 (ja) * | 1998-07-24 | 2010-09-08 | ルネサスエレクトロニクス株式会社 | 同期型半導体記憶装置 |
| JP4521922B2 (ja) * | 2000-03-17 | 2010-08-11 | Okiセミコンダクタ株式会社 | 組み込み型メモリ試験回路 |
| JP4808856B2 (ja) * | 2001-04-06 | 2011-11-02 | 富士通セミコンダクター株式会社 | 半導体記憶装置 |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51147924A (en) * | 1975-06-13 | 1976-12-18 | Fujitsu Ltd | Memory unit |
| JPS53120234A (en) * | 1977-03-30 | 1978-10-20 | Toshiba Corp | Semiconductor memory |
-
1981
- 1981-04-25 JP JP56063004A patent/JPS57179997A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57179997A (en) | 1982-11-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4686456A (en) | Memory test circuit | |
| US5636163A (en) | Random access memory with a plurality amplifier groups for reading and writing in normal and test modes | |
| US6046946A (en) | Method and apparatus for testing multi-port memory using shadow read | |
| US4675850A (en) | Semiconductor memory device | |
| JPH0463480B2 (de) | ||
| JPH0215960B2 (de) | ||
| US5717643A (en) | Semiconductor memory device with testing function | |
| JPH1074396A (ja) | 半導体記憶装置 | |
| JPH02146195A (ja) | 半導体記憶装置 | |
| JPS63106998A (ja) | テスト回路を有する半導体メモリ | |
| JPH05249196A (ja) | 半導体記憶装置 | |
| JPS63257999A (ja) | 半導体記憶装置 | |
| US4458338A (en) | Circuit for checking memory cells of programmable MOS-integrated semiconductor memories | |
| JPH05210998A (ja) | 半導体メモリ装置 | |
| JPH03283199A (ja) | 複数ビット並列テスト回路を具備する半導体メモリ | |
| JPH0687360B2 (ja) | 半導体記憶装置 | |
| US5920573A (en) | Method and apparatus for reducing area and pin count required in design for test of wide data path memories | |
| US7254756B2 (en) | Data compression read mode for memory testing | |
| JPH0325872B2 (de) | ||
| US6473345B2 (en) | Semiconductor memory device which can be simultaneously tested even when the number of semiconductor memory devices is large and semiconductor wafer on which the semiconductor memory devices are formed | |
| US5293598A (en) | Random access memory with a plurality of amplifier groups | |
| US5337287A (en) | Dual port semiconductor memory device | |
| RU2084972C1 (ru) | Способ записи данных при тестировании устройства памяти и устройство для проверки памяти | |
| US20040044932A1 (en) | Output data compression scheme using tri-state | |
| JPH01253900A (ja) | 半導体記憶装置のテスト方式 |